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PDF GS81313LT36GK Data sheet ( Hoja de datos )

Número de pieza GS81313LT36GK
Descripción 144Mb SigmaDDR-IIIe Burst of 2 ECCRAM
Fabricantes GSI Technology 
Logotipo GSI Technology Logotipo



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GS81313LT18/36GK-833/714/625
260-Pin BGA
Com & Ind Temp
HSTL I/O
144Mb SigmaDDR-IIIe™
Burst of 2 ECCRAM™
Up to 833 MHz
1.25V ~ 1.3V VDD
1.2V ~ 1.3V VDDQ
Features
• 4Mb x 36 and 8Mb x 18 organizations available
• 833 MHz maximum operating frequency
• 833 MT/s peak transaction rate (in millions per second)
• 60 Gb/s peak data bandwidth (in x36 devices)
• Common I/O DDR Data Bus
• Non-multiplexed SDR Address Bus
• One operation - Read or Write - per clock cycle
• Burst of 2 Read and Write operations
• 3 cycle Read Latency
• On-chip ECC with virtually zero SER
• 1.25V ~ 1.3V core voltage
• 1.2V ~ 1.3V HSTL I/O interface
• Configurable ODT (on-die termination)
• ZQ pin for programmable driver impedance
• ZT pin for programmable ODT impedance
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 260-pin, 14 mm x 22 mm, 1 mm ball pitch, 6/6 RoHS-
compliant BGA package
SigmaDDR-IIIeFamily Overview
SigmaDDR-IIIe ECCRAMs are the Common I/O half of the
SigmaQuad-IIIe/SigmaDDR-IIIe family of high performance
ECCRAMs. Although very similar to GSI's second generation
of networking SRAMs (the SigmaQuad-II/SigmaDDR-II
family), these third generation devices offer several new
features that help enable significantly higher performance.
Clocking and Addressing Schemes
The GS81313LT18/36GK SigmaDDR-IIIe ECCRAMs are
synchronous devices. They employ three pairs of positive and
negative input clocks; one pair of master clocks, CK and CK,
and two pairs of write data clocks, KD[1:0] and KD[1:0]. All
six input clocks are single-ended; that is, each is received by a
dedicated input buffer.
CK and CK are used to latch address and control inputs, and to
control all output timing. KD[1:0] and KD[1:0] are used solely
to latch data inputs.
Each internal read and write operation in a SigmaDDR-IIIe B2
ECCRAM is two times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore, the address
field of a SigmaDDR-IIIe B2 ECCRAM is always one address
pin less than the advertised index depth (e.g. the 8M x 18 has
4M addressable index).
On-Chip Error Correction Code
GSI's ECCRAMs implement an ECC algorithm that detects
and corrects all single-bit memory errors, including those
induced by SER events such as cosmic rays, alpha particles,
etc. The resulting Soft Error Rate of these devices is
anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude
improvement over comparable SRAMs with no on-chip ECC,
which typically have an SER of 200 FITs/Mb or more.
All quoted SER values are at sea level in New York City.
Speed Grade
-833
-714
-625
Parameter Synopsis
Max Operating Frequency
833 MHz
714 MHz
625 MHz
Read Latency
3 cycles
3 cycles
3 cycles
VDD
1.2V to 1.35V
1.2V to 1.35V
1.2V to 1.35V
Rev: 1.13 7/2016
1/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology

1 page




GS81313LT36GK pdf
GS81313LT18/36GK-833/714/625
Symbol
PZT[1:0]
VDD
VDDQ
VREF
VSS
TCK
TMS
TDI
TDO
MCH
MCL
NC
NUI
NUIO
Description
ODT Configuration Select — Set the ODT state for various combinations of input groups when MZT[1:0] =
01 or 10. Must be tied High or Low.
PZT[1:0] = 00: enables ODT on write data only.
PZT[1:0] = 01: enables ODT on write data and input clocks.
PZT[1:0] = 10: enables ODT on write data, address, and control.
PZT[1:0] = 11: enables ODT on write data, input clocks, address, and control.
Core Power Supply
I/O Power Supply
Input Reference Voltage — Input buffer reference voltage.
Ground
JTAG Clock — Weakly pulled Low internally.
JTAG Mode Select — Weakly pulled High internally.
JTAG Data Input — Weakly pulled High internally.
JTAG Data Output
Must Connect High — May be tied to VDDQ directly or via a 1kresistor.
Must Connect Low — May be tied to VSS directly or via a 1kresistor.
No Connect — There is no internal chip connection to these pins. They may be left unconnected, or tied/
driven High or Low.
Not Used Input — There is an internal chip connection to these input pins, but they are unused by the
device. They are pulled Low internally. They may be left unconnected or tied/driven Low. They should not be
tied/driven High.
Not Used Input/Output — There is an internal chip connection to these I/O pins, but they are unused by the
device. The drivers are tri-stated internally. They are pulled Low internally. They may be left unconnected or
tied/driven Low. They should not be tied/driven High.
Type
Input
Input
Input
Input
Output
Input
Input
Input
I/O
Rev: 1.13 7/2016
5/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology

5 Page





GS81313LT36GK arduino
GS81313LT18/36GK-833/714/625
NOPr and NOPw Requirements
The number of NOPw and NOPr needed during Write -> Read transitions, and the number of NOPr and NOPw needed during Read
-> Write transitions, are as follows:
Write -> Read Transition
Read -> Write Transition
NOPw (after Write)
min typ
00
NOPr (before Read)
min typ
0 1~2
NOPr (after Read)
min typ
2 3~4
NOPw (before Write)
min typ
3 4~5
Notes:
1. Min NOPw after Write (0) ensures that the SRAM disables DQ ODT 2.5 cycles after it latches the last piece of write data. Typ
NOPw is the same as Min NOPw because it is sufficient to ensure that the controller stops driving the last piece of write data
before SRAM DQ ODT disable reaches it (as the result of a subsequent NOPr or Read), regardless of SRAM tKQ, prop delay
between SRAM and controller, and operating frequency.
2. Min NOPr before Read (0) ensures that the SRAM drives Low 1 cycle before it begins driving the first piece of read data. Typ
NOPr is greater than Min NOPr in order to ensure that the controller enables DQ ODT after SRAM Low drive reaches it (and
before the SRAM drives the first piece of read data), accounting for SRAM tKQ, prop delay between SRAM and controller, and
operating frequency.
3. Min NOPr after Read (2) ensures that the SRAM drives Low for 1 cycle after it stops driving the last piece of read data and before
it enables DQ ODT (as the result of a subsequent NOPw). Typ NOPr is greater than Min NOPr in order to ensure that the controller
disables DQ ODT after SRAM Low drive reaches is (and before the SRAM enables DQ ODT), accounting for SRAM tKQ, prop
delay between SRAM and controller, and operating frequency.
4. Min NOPw before Write (3) ensures that the SRAM enables DQ ODT 1 cycle before it latches the first piece of write data. Typ
NOPw is greater than Min NOPw in order to ensure that the controller begins driving the first piece of write data after SRAM
DQ ODT enable reaches it, accounting for SRAM tKQ, prop delay between SRAM and controller, and operating frequency.
Write1
NOPr1
DQ ODT Control Timing Diagram
Read1 NOPr2 NOPr3 NOPr4 NOPw1
NOPw2
NOPw3
NOPw4
Write2
CK, KD
SA A1
A2
A3
LD
R/W
tKHDQT
tKHQV
tKHDQT
DQ D11 D12
Q21 Q22
D31
CQ
Note: In the diagram above, the controller is disabling its DQ ODT except from the beginning of NOPr4 to the beginning of NOPw3.
And while it is disabling its DQ ODT, the controller is driving DQ Low when it isn’t driving write data. Whereas, the SRAM is
enabling its DQ ODT except from the beginning of NOPr2 to the beginning of NOPw3. And while it is disabling its DQ ODT, the
SRAM is driving DQ Low when it isn’t driving read data.
Rev: 1.13 7/2016
11/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology

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