DataSheet.es    


PDF GS81302R09GE Data sheet ( Hoja de datos )

Número de pieza GS81302R09GE
Descripción 144Mb SigmaDDR-II Burst of 4 SRAM
Fabricantes GSI Technology 
Logotipo GSI Technology Logotipo



Hay una vista previa y un enlace de descarga de GS81302R09GE (archivo pdf) en la parte inferior de esta página.


Total 30 Páginas

No Preview Available ! GS81302R09GE Hoja de datos, Descripción, Manual

GS81302R08/09/18/36E-375/350/333/300/250
165-Bump BGA
Commercial Temp
Industrial Temp
144Mb SigmaDDRTM-II
Burst of 4 SRAM
375 MHz–250 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
Features
• Simultaneous Read and Write SigmaDDR™ Interface
• Common I/O bus
• JEDEC-standard pinout and package
• Double Data Rate interface
• Byte Write (x36 and x18) and Nybble Write (x8) function
• Burst of 4 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation with self-timed Late Write
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• Pin-compatible with present 9Mb, 18Mb, 36Mb and 72Mb
devices
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
SigmaDDRFamily Overview
The GS81302R08/09/18/36E are built in compliance with the
SigmaDDR-II SRAM pinout standard for Common I/O
synchronous SRAMs. They are 150,994,944-bit (144Mb)
SRAMs. The GS81302R08/09/18/36E SigmaDDR-II SRAMs
are just one element in a family of low power, low voltage
HSTL I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS81302R08/09/18/36E SigmaDDR-II SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer. The device also allows the user to manipulate the
output register clock inputs quasi independently with the C and
C clock inputs. C and C are also independent single-ended
clock inputs, not differential inputs. If the C clocks are tied
high, the K clocks are routed internally to fire the output
registers instead.
Each internal read and write operation in a SigmaDDR-II B4
RAM is four times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed.
When a new address is loaded into a x18 or x36 version of the
part, A0 and A1 are used to initialize the pointers that control
the data multiplexer / de-multiplexer so the RAM can perform
"critical word first" operations. From an external address point
of view, regardless of the starting point, the data transfers
always follow the same linear sequence {00, 01, 10, 11} or
{01, 10, 11, 00} or {10, 11, 00, 01} or {11, 00, 01, 10} (where
the digits shown represent A1, A0).
Unlike the x18 and x36 versions, the input and output data
multiplexers of the x8 and x9 versions are not preset by
address inputs and therefore do not allow "critical word first"
operations. The address fields of the x8 and x9 SigmaDDR-II
B4 RAMs are two address pins less than the advertised index
depth (e.g., the 16M x 8 has a 4M addressable index, and A0
and A1 are not accessible address pins).
Parameter Synopsis
tKHKH
tKHQV
-375
2.66 ns
0.45 ns
-350
2.86 ns
0.45 ns
-333
3.0 ns
0.45 ns
-300
3.3 ns
0.45 ns
-250
4.0 ns
0.45 ns
Rev: 1.03b 12/2011
1/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

1 page




GS81302R09GE pdf
GS81302R08/09/18/36E-375/350/333/300/250
16M x 8 SigmaDDR-II SRAM—Top View
1 2 3 4 5 6 7 8 9 10 11
A CQ SA SA R/W NW1 K SA LD SA SA CQ
B
NC
NC
NC
SA
NC/SA
(288Mb)
K
NW0 SA
NC
NC DQ3
C NC NC NC VSS SA NC SA VSS NC NC NC
D NC NC NC VSS VSS VSS VSS VSS NC NC NC
E NC NC DQ4 VDDQ VSS VSS VSS VDDQ NC NC DQ2
F
NC
NC
NC
VDDQ
VDD
VSS
VDD VDDQ NC
NC
NC
G NC NC DQ5 VDDQ VDD VSS VDD VDDQ NC NC NC
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD VDDQ NC
DQ1
NC
K
NC
NC
NC
VDDQ
VDD
VSS
VDD VDDQ NC
NC
NC
L
NC
DQ6
NC
VDDQ
VSS
VSS
VSS VDDQ NC
NC DQ0
M NC NC NC VSS VSS VSS VSS VSS NC NC NC
N NC NC NC VSS SA SA SA VSS NC NC NC
P NC NC DQ7 SA SA C SA SA NC NC NC
R
TDO TCK
SA
SA
SA
C
SA SA SA TMS TDI
11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch
Notes:
1. Unlike the x36 and x18 versions of this device, the x8 and x9 versions do not give the user access to A0 and A1. SA0 and SA1 are set to
0 at the beginning of each access.
2. NW0 controls writes to DQ0:DQ3; NW1 controls writes to DQ4:DQ7.
3. B5 is the expansion address.
Rev: 1.03b 12/2011
5/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

5 Page





GS81302R09GE arduino
GS81302R08/09/18/36E-375/350/333/300/250
Burst of 4 Nybble Write Clock Truth Table
NW NW NW NW
Current Operation
D
K
(tn+1)
K
(tn+1½)
K
(tn+2)
K
(tn+2½)
TTTT
TFFF
K
(tn)
Write
Dx stored if NWn = 0 in all four data transfers
Write
Dx stored if NWn = 0 in 1st data transfer only
K
(tn+1)
D0
D0
F
T
F
F
Write
Dx stored if NWn = 0 in 2nd data transfer only
X
F
F
T
F
Write
Dx stored if NWn = 0 in 3rd data transfer only
X
F
F
F
T
Write
Dx stored if NWn = 0 in 4th data transfer only
X
F
F
F
F
Write Abort
No Dx stored in any of the four data transfers
X
Notes:
1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
2. If one or more NWn = 0, then NW = “T”, else NW = “F”.
D
K
(tn+1½)
D2
X
D1
X
X
X
D
K
(tn+2)
D3
X
X
D2
X
X
D
K
(tn+2½)
D4
X
X
X
D3
X
Rev: 1.03b 12/2011
11/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

11 Page







PáginasTotal 30 Páginas
PDF Descargar[ Datasheet GS81302R09GE.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
GS81302R09GE144Mb SigmaDDR-II Burst of 4 SRAMGSI Technology
GSI Technology

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar