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PDF GS81302S08GE Data sheet ( Hoja de datos )

Número de pieza GS81302S08GE
Descripción 144Mb SigmaSIO DDR -II Burst of 2 SRAM
Fabricantes GSI Technology 
Logotipo GSI Technology Logotipo



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No Preview Available ! GS81302S08GE Hoja de datos, Descripción, Manual

GS81302S08/09/18/36E-375/350/333/300/250
165-Bump BGA
Commercial Temp
Industrial Temp
144Mb SigmaSIOTM DDR -II
Burst of 2 SRAM
375 MHz–250 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
Features
• Simultaneous Read and Write SigmaSIO™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• DLL circuitry for wide output data valid window and future
frequency scaling
• Burst of 2 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ mode pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
SigmaSIOFamily Overview
GS81302S08/09/18/36 are built in compliance with the
SigmaSIO DDR-II SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 150,994,944-bit (144Mb)
SRAMs. These are the first in a family of wide, very low
voltage HSTL I/O SRAMs designed to operate at the speeds
needed to implement economical high performance
networking systems.
Clocking and Addressing Schemes
A Burst of 2 SigmaSIO DDR-II SRAM is a synchronous
device. It employs dual input register clock inputs, K and K.
The device also allows the user to manipulate the output
register clock input quasi independently with dual output
register clock inputs, C and C. If the C clocks are tied high, the
Bottom View
165-Bump, 15 mm x 17 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
JEDEC Std. MO-216, Variation CAB-1
K clocks are routed internally to fire the output registers
instead. Each Burst of 2 SigmaSIO DDR-II SRAM also
supplies Echo Clock outputs, CQ and CQ, which are
synchronized with read data output. When used in a source
synchronous clocking scheme, the Echo Clock outputs can be
used to fire input registers at the data’s destination.
Each internal read and write operation in a SigmaSIO DDR-II
B2 RAM is two times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore, the address
field of a SigmaSIO DDR-II B2 is always one address pin less
than the advertised index depth (e.g., the 16M x 8 has an 8M
addressable index).
Parameter Synopsis
tKHKH
tKHQV
-375
2.66 ns
0.45 ns
-350
2.86 ns
0.45 ns
-333
3.0 ns
0.45 ns
-300
3.3 ns
0.45 ns
-250
4.0 ns
0.45 ns
Rev: 1.03b 12/2011
1/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

1 page




GS81302S08GE pdf
GS81302S08/09/18/36E-375/350/333/300/250
4M x 36 SigmaQuad SRAM—Top View
123456789
A
CQ
NC/SA
(288Mb)
SA
R/W BW2
K
BW1 LD
SA
B Q27 Q18 D18 SA BW3 K BW0 SA D17
C D27 Q28 D19 VSS SA SA SA VSS D16
D D28 D20 Q19 VSS VSS VSS VSS VSS Q16
E
Q29
D29
Q20 VDDQ VSS
VSS
VSS
VDDQ
Q15
F
Q30
Q21
D21
VDDQ
VDD
VSS
VDD
VDDQ
D14
G
D30
D22
Q22 VDDQ VDD
VSS
VDD
VDDQ
Q13
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
J
D31
Q31
D23
VDDQ
VDD
VSS
VDD
VDDQ
D12
K
Q32
D32
Q23 VDDQ VDD
VSS
VDD
VDDQ
Q12
L
Q33
Q24
D24 VDDQ VSS
VSS
VSS
VDDQ
D11
M D33 Q34 D25 VSS VSS VSS VSS VSS D10
N D34 D26 Q25 VSS SA SA SA VSS Q10
P
Q35 D35 Q26
SA
SA
C
SA SA Q9
R
TDO TCK
SA
SA
SA
C
SA SA SA
11 x 15 Bump BGA—15 x 17 mm2 Body—1 mm Bump Pitch
Notes:
1. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17.
2. BW2 controls writes to D18:D26. BW3 controls writes to D27:D35.
3. A2 is the expansion address.
10
SA
Q17
Q7
D15
D6
Q14
D13
VREF
Q4
D3
Q11
Q1
D9
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
Rev: 1.03b 12/2011
5/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

5 Page





GS81302S08GE arduino
GS81302S08/09/18/36E-375/350/333/300/250
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaSIO DDR-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected
to VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be
5X the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching
with a vendor-specified tolerance is between 175Ω and 350Ω. Periodic readjustment of the output driver impedance is necessary as
the impedance is affected by drifts in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for
drifts in supply voltage and temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts
again. Each impedance evaluation may move the output driver impedance level one step at a time towards the optimum level. The
output driver is implemented with discrete binary weighted impedance steps.
Separate I/O Burst of 2 Sigma SIO-II SRAM Truth Table
A LD R/W
Current
Operation
DD
KKK
(tn) (tn) (tn)
K
(tn)
K
(tn + 1)
K
(tn + 1½)
X1X
Deselect
XX
V01
Read
XX
V00
Write
D0 D1
Notes:
1. “1” = input “high”; “0” = input “low”; “V” = input “valid”; “X” = input “don’t care”
2. Q0 and Q1 indicate the first and second pieces of output data transferred during Read operations.
3. D0 and D1 indicate the first and second pieces of input data transferred during Write operations.
4. Users should not clock in metastable addresses.
Q
K
(tn + 1½)
Hi-Z
Q0
Hi-Z
Q
K
(tn + 2)
Hi-Z
Q1
Hi-Z
Rev: 1.03b 12/2011
11/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

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