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PDF GS81302TT07GE Data sheet ( Hoja de datos )

Número de pieza GS81302TT07GE
Descripción 144Mb SigmaDDR-II+ Burst of 2 SRAM
Fabricantes GSI Technology 
Logotipo GSI Technology Logotipo



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No Preview Available ! GS81302TT07GE Hoja de datos, Descripción, Manual

GS81302TT07/10/19/37E-450/400/350/333/300
165-Bump BGA
Commercial Temp
Industrial Temp
144Mb SigmaDDRTM-II+
Burst of 2 SRAM
450 MHz–300 MHz
1.8 V VDD
1.8 V or 1.5 V I/O
Features
• 2.0 Clock Latency
• Simultaneous Read and Write SigmaDDR™ Interface
• Common I/O bus
• JEDEC-standard pinout and package
• Double Data Rate interface
• Byte Write controls sampled at data-in time
• Burst of 2 Read and Write
• Dual-Range On-Die Termination (ODT) on Data (D), Byte
Write (BW), and Clock (K, K) inputs
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation with self-timed Late Write
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• Data Valid pin (QVLD) Support
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
SigmaDDRFamily Overview
The GS81302TT07/10/19/37E are built in compliance with the
SigmaDDR-II+ SRAM pinout standard for Common I/O
synchronous SRAMs. They are 150,994,944-bit (144Mb)
SRAMs. The GS81302TT07/10/19/37E SigmaDDR-II+
SRAMs are just one element in a family of low power, low
voltage HSTL I/O SRAMs designed to operate at the speeds
needed to implement economical high performance
networking systems.
Clocking and Addressing Schemes
The GS81302TT07/10/19/37E SigmaDDR-II+ SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
Each internal read and write operation in a SigmaDDR-II+ B2
RAM is two times wider than the device I/O bus. An input data
bus de-multiplexer is used to accumulate incoming data before
it is simultaneously written to the memory array. An output
data multiplexer is used to capture the data produced from a
single memory array read and then route it to the appropriate
output drivers as needed. Therefore, the address field of a
SigmaDDR-II+ B2 RAM is always one address pin less than
the advertised index depth (e.g., the 16M x 8 has an 8M
addressable index).
Parameter Synopsis
tKHKH
tKHQV
-450
2.2 ns
0.45 ns
-400
2.5 ns
0.45 ns
-350
2.86 ns
0.45 ns
-333
3.0 ns
0.45 ns
-300
3.3 ns
0.45 ns
Rev: 1.00a 11/2011
1/30
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

1 page




GS81302TT07GE pdf
GS81302TT07/10/19/37E-450/400/350/333/300
4M x 36 SigmaDDR-II+ SRAM—Top View
1 2 3 4 5 6 7 8 9 10 11
A CQ SA SA R/W BW2 K BW1 LD SA SA CQ
B
NC DQ27 DQ18 SA BW3
K
BW0
SA
NC
(288Mb)
NC
DQ8
C NC NC DQ28 VSS SA NC SA VSS NC DQ17 DQ7
D NC DQ29 DQ19 VSS VSS VSS VSS VSS NC NC DQ16
E
NC
NC
DQ20
VDDQ
VSS
VSS
VSS VDDQ NC DQ15 DQ6
F
NC
DQ30 DQ21
VDDQ
VDD
VSS
VDD VDDQ NC
NC DQ5
G
NC
DQ31 DQ22
VDDQ
VDD
VSS
VDD VDDQ NC
NC DQ14
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
DQ32
VDDQ
VDD
VSS
VDD VDDQ NC DQ13 DQ4
K
NC
NC
DQ23
VDDQ
VDD
VSS
VDD VDDQ NC DQ12 DQ3
L
NC
DQ33
DQ24
VDDQ
VSS
VSS
VSS VDDQ NC
NC DQ2
M
NC
NC DQ34 VSS VSS VSS VSS
VSS
NC
DQ11
DQ1
N
NC DQ35 DQ25 VSS
SA
SA
SA
VSS NC
NC DQ10
P NC NC DQ26 SA SA QVLD SA SA NC DQ9 DQ0
R
TDO TCK
SA
SA
SA ODT SA
SA
SA TMS TDI
11 x 15 Bump BGA—15 x 17 mm2 Body—1 mm Bump Pitch
Notes:
3. BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ17; BW2 controls writes to DQ18:DQ26; BW3 controls writes to
DQ27:DQ35
4. B9 is the expansion address.
Rev: 1.00a 11/2011
5/30
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

5 Page





GS81302TT07GE arduino
GS81302TT07/10/19/37E-450/400/350/333/300
Burst of 2 Nybble Write Clock Truth Table
NW NW
Current Operation
K
(tn + 1)
T
T
K
(tn + 1½)
T
F
K
(tn)
Write
Dx stored if NWn = 0 in both data transfers
Write
Dx stored if NWn = 0 in 1st data transfer only
FT
Write
Dx stored if NWn = 0 in 2nd data transfer only
FF
Write Abort
No Dx stored in either data transfer
Notes:
1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
2. If one or more NWn = 0, then NW = “T”, else NW = “F”.
D
K
(tn + 1)
D1
D1
X
X
D
K
(tn + 1½)
D2
X
D2
X
x36 Byte Write Enable (BWn) Truth Table
BW0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
BW1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
BW2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
BW3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
D0–D8
Don’t Care
Data In
Don’t Care
Data In
Don’t Care
Data In
Don’t Care
Data In
Don’t Care
Data In
Don’t Care
Data In
Don’t Care
Data In
Don’t Care
Data In
D9–D17
Don’t Care
Don’t Care
Data In
Data In
Don’t Care
Don’t Care
Data In
Data In
Don’t Care
Don’t Care
Data In
Data In
Don’t Care
Don’t Care
Data In
Data In
D18–D26
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Data In
Data In
Data In
Data In
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Data In
Data In
Data In
Data In
D27–D35
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Data In
Data In
Data In
Data In
Data In
Data In
Data In
Data In
Rev: 1.00a 11/2011
11/30
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

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