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Número de pieza SC1109BSTR
Descripción Synchronous PWM Controller
Fabricantes Semtech 
Logotipo Semtech Logotipo



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SC1109
Synchronous PWM Controller with Dual
Low Dropout Regulator Controllers
POWER MANAGEMENT
Description
Features
The SC1109 was designed for the latest high speed
motherboards. It combines a synchronous voltage mode
controller (switching section) with two low-dropout linear
regulator controllers. The voltage mode controller pro-
vides the power supply for the system AGTL bus. The Dual
linear controllers power the chip set and clock circuitry.
The SC1109A switching section features lossless current
sensing, while SC1109C provides programmable over cur-
rent limit. SC1109 also utilizes latched driver outputs for
enhanced noise immunity. SC1109A and SC1109C oper-
ate at a fixed frequency of 200kHz, and the SC1109B is
available at a fixed frequency of 500kHz. The VTT output
voltage is internally fixed at 1.2V
The SC1109 linear sections are low dropout regulators
designed to track the 3.3V power supply when it turns on
or off. The voltage for the linear controllers LDO1, and LDO2
are 1.8V/1.5V.
Typical Application Circuit
‹ Dual linear controllers
‹ LDOs track input voltage within 200mV (function of
the MOSFETs used) until regulation
‹ Integrated drivers
‹ Power good signal (SC1109A, SC1109B)
‹ Soft start
‹ Lossless current sense
‹ Programmable over current limit (SC1109C)
‹ 200kHz (SC1109A, SC1109C), and 500kHz (SC1109B)
fixed frequency.
Applications
‹ Pentium® III Motherboards
‹ Triple power supplies
12V IN
5V STBY
5V IN
POWER GOOD
3.3V IN
C2 C3
2x1500uF + 0.1uF
C9
0.1uF
C5
0.1uF
SC1109ACSTR or SC1109BCSTR
11 VCC
STBY 3
4
C6
0.1uF
5
BCAP+
BCAP-
BST
DH
PHASE
10
9
7
R1 2.2
14 SS/EN
12 PWRGD
DL 8
R2 2.2
13 VOSENSE GND 6
15 GATE2
GATE1 2
16 LDOS2 LDOS1 1
C4
0.1uF
U1
C1
0.1uF
Q1
MOSFET N
L1 4uH
C7
Q2 3x1500uF
MOSFET N
+
1.2V 6A
C8
0.1uF
VTT
+
C10
330uF
Q3
MOSFET N
+
C11
330uF
LDO2 = 1.5V
Q4
MOSFET N
+
C12
330uF
LDO1 = 1.8V
12V IN
5V STBY
5V IN
C2 C3
2x1500uF + 0.1uF
C13
1nF
OCSET
R3
TBD
C9
0.1uF
C5
0.1uF
11 VCC
U1
STBY 3
4
C6
0.1uF
5
BCAP+
BCAP-
BST
DH
PHASE
10
9
7
R1 2.2
14 SS/EN
12 OCSET
DL 8
R2 2.2
13 VOSENSE GND 6
15 GATE2
GATE1 2
16 LDOS2
LDOS1 1
SC1109CCSTR
C4
0.1uF
C1
0.1uF
Q1
MOSFET N
L1 4uH
C7
Q2 3x1500uF
MOSFET N
+
1.2V 6A
C8
0.1uF
VTT
3.3V IN
+
C10
330uF
Q3
MOSFET N
+
C11
330uF
LDO2 = 1.5V
Q4
MOSFET N
+
C12
330uF
LDO1 = 1.8V
Revision: May 13, 2004
1
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1 page




SC1109BSTR pdf
SC1109
POWER MANAGEMENT
Block Diagram
SC1109A/B
VCC
1.2V
Bandgap
-10%
+10%
VBG
UVLO
+
-
PWRGD
VOSENSE
SS/EN
VCC VBG
10uA
-
+
-
+
- ERROR AMP
+
0.8V
SS/EN
0.6V
+
-
+
-
OSCILLATOR
PWM
-
+
SET DOMINATES
S
Q
R
HICCUP LATCH
2uA
5VSTBY
STBY
BCAP+
CHARGE
PUMP
OVER
CURRENT
200mV
+
-
HIGH
SIDE
DRIVE
R
Q
S
SHOOT
THRU
CONTROL
VCC
LOW
SIDE
DRIVE
FAULT
5VSTBY
OSCILLATOR
LOW SIDE OFF
5VSTBY
VBG +
-
5VSTBY
VBG +
-
BCAP-
BST
DH
PHASE
DL
GND
GATE2
LDOS2
GATE1
LDOS1
SC1109C
VCC
1.2V
Bandgap
VBG
UVLO
+
-
OVER
CURRENT
+
-
160uA
OSCILLATOR
VOSENSE
SS/EN
VCC VBG
10uA
- ERROR AMP
+
0.8V
SS/EN
0.6V
+
-
+
-
PWM
-
+
SET DOMINATES
S
Q
R
HICCUP LATCH
2uA
5VSTBY
R
Q
S
FAULT
STBY
BCAP+
CHARGE
PUMP
5VSTBY
OSCILLATOR
HIGH
SIDE
DRIVE
SHOOT
THRU
CONTROL
VCC
LOW
SIDE
DRIVE
LOW SIDE OFF
5VSTBY
VBG +
-
5VSTBY
VBG +
-
BCAP-
Marking Information
OCSET
BST
DH
PHASE
DL
GND
GATE2
LDOS2
GATE1
LDOS1
SC1109ACS
yyww
xxxxx
SC1109A
SC1109BS
yyww
xxxxx
SC1109B
SC1109CS
yyww
xxxxx
SC1109C
yyww = Datecode (Example: 9912)
xxxxx = Semtech Lot # (Example: 90101)
2004 Semtech Corp.
5
www.semtech.com

5 Page





SC1109BSTR arduino
SC1109
POWER MANAGEMENT
Application Information (Cont.)
or more generally,
PSW
=
IO
VIN
(tr +
4
t f ) fOSC
c) Body diode recovery losses are more difficult to esti-
mate, but to a first approximation, it is reasonable to
assume that the stored charge on the bottom FET body
diode will be moved through the top FET as it starts to
turn on. The resulting power dissipation in the top FET
will be:
P RR = Q RR V IN f OSC
To a first order approximation, it is convenient to only
consider conduction losses to determine FET suitability.
For a 5V in; 2.8V out at 14.2A requirement, typical FET
losses would be:
Using 1.5X Room temp RDS(ON) to allow for temperature
rise.
FET Type
IRL3402S
IRL2203
Si4410
RDS(on) (m)
15
10.5
20
PD(W)
1.33
0.93
1.77
Package
D2PAK
D2PAK
SO-8
Each of the package types has a characteristic thermal
impedance, for the TO-220 package, thermal impedance
is mostly determined by the heatsink used. For the sur-
face mount packages on double sided FR4, 2 oz printed
circuit board material, thermal impedances of 40oC/W
for the D2PAK and 80oC/W for the SO-8 are readily achiev-
able. The corresponding temperature rise is detailed be-
low:
Temperature rise ( 0C)
FET Type
IRL3402S
IRL2203
Si4410
RDS(on) (m)
15
10.5
20
PD(W)
1.69
1.19
2.26
Package
D2PAK
D2PAK
SO-8
FET Type
IRL3402S
IRL2203
Si4410
Top FET
67.6
47.6
180.8
Bottom FET
53.2
37.2
141.6
BOTTOM FET - Bottom FET losses are almost entirely
due to conduction. The body diode is forced into conduc-
tion at the beginning and end of the bottom switch con-
duction period, so when the FET turns on and off, there
is very little voltage across it, resulting in low switching
losses. Conduction losses for the FET can be determined
by:
P COND
=
I
2
O
R DS
( on )
(1
δ)
For the example above:
It is apparent that single SO-8 Si4410 are not adequate
for this application, but by using parallel pairs in each
position, power dissipation will be approximately halved
and temperature rise reduced by a factor of 4.
INPUT CAPACITORS - since the RMS ripple current in the
input capacitors may be as high as 50% of the output
current, suitable capacitors must be chosen accordingly.
Also, during fast load transients, there may be restric-
tions on input di/dt. These restrictions require useable
energy storage within the converter circuitry, either as
extra output capacitance or, more usually, additional in-
put capacitors. Choosing low ESR input capacitors will
help maximize ripple rating for a given size.
2004 Semtech Corp.
11
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