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PDF UT01VS33D Data sheet ( Hoja de datos )

Número de pieza UT01VS33D
Descripción Voltage Supervisor
Fabricantes Aeroflex Circuit Technology 
Logotipo Aeroflex Circuit Technology Logotipo



Total 15 Páginas
		
UT01VS33D Hoja de datos, Descripción, Manual
Standard Products
UT01VS33D Voltage Supervisor
Data Sheet
July 28, 2014
www.aeroflex.com/voltsupv
FEATURES
3.15V to 3.6V Operating voltage range
Power supply (VDD) monitor set by the internal voltage
reference at 3.08V
Precision Input Voltage Monitor using an internal 0.6V
voltage reference
Watchdog Timer Circuit monitoring activity on WDI input
- Nominal timeout 1.6s
RESET_OD output responding to the VDD monitor and the
manual reset input MR
- Nominal RESET_OD pulse width 200ms
RESET_OD level valid for VDD>=1.2V
Operating Temperature Range -55oC to +125oC
Low Power, Typical 400uA
Operational environment:
- Total dose: 300 krad(Si)
- SEL Immune: <110 MeV-cm2/mg @125oC
- SET Immune: <80 MeV-cm2/mg
Packaging options:
- 8-lead dual-in-line flatpack
Standard Microelectronics Drawing 5962-11213
- QML Q and V
INTRODUCTION
The UT01VS33D’s function is to monitor vital supply and signal
voltages in microprocessor systems. It provides for safe reset
during power up, power down and brownout conditions by using
an internal precision voltage reference.
The UT01VS33D monitors activity at an independent watchdog
input by employing an internal timer and a watchdog output that
goes low if the input is not toggled within 1.6s. It provides for
precision voltage threshold detection on an independent voltage
input which could be used for battery or supply-low monitoring
of a supply voltage other than VDD.
The UT01VS33D includes an active low manual reset with an
open drain output.
APPLICATIONS
Voltage Supervisor function for various systems including
microprocessors, microcontrollers, DSPs and FPGAs
Critical battery and power supply monitoring
Replacement of older discrete solutions to improve reliability,
accuracy and reduce complexity of the systems
MR
RESET &
DIGITAL CONTROL
VDD +
WDI TIMER
3.08 V
GND
0.6 V
VREF
WDI TRANSITION
DETECTOR
OSC
PFI +
WDO
RESET_OD
WDI
PFO
Figure 1. UT01VS33D Functional Block Diagram
1

1 page

UT01VS33D pdf
ELECTRICAL CHARACTERISTICS 1,2
(VDD = 3.15V to 3.6V: -55°C < TC < +125°C)
SYMBOL
PARAMETER
CONDITION
Power Supply
IDD VDD supply current
VDD=3.6V
Digital Inputs and Outputs (MR, RESET_OD, WDI, WDO, PFO)
VIL_WDI
Digital input low
VDD=3.15V
VIH_WDI
Digital input high
VDD=3.6V
VIL_MR
Manual reset input low
VDD=3.15V
VIH_MR
Manual reset input high
VDD=3.6V
VOL_WDO
Digital output low
VDD=3.15V, ISINK= 500A
VOL_RESET_OD RESET_OD digital output low VDD=3.15V, ISINK=1.2mA
VOL_PFO
PFO digital output low
VDD=3.15V, ISINK=1.2mA
VOH3
Digital output high
VDD=3.15V, ISOURCE =500A
Timing and Threshold Voltages
tRST-ASSRT4
VDD falling reset assertion
VDD < 3.0V
tRS Reset pulse width
VDD=3.15V
tWD Watchdog time-out period
VDD=3.6V
tWP
Watchdog input pulse width
VDD=3.15V
VRT Reset threshold voltage
VDD=3.15V
VRTHYS
Reset threshold voltage hysteresis
tMR Manual reset (MR) input pulse VDD=3.15V
width
tMD Manual reset (MR) to reset out VDD=3.15V
delay
Analog Input PFI
IPFI4
Threshold detector input (PFI)
current
VDD=3.6V
VPFI Threshold detector input (PFI) VDD=3.3V
threshold voltage
IMR
Manual reset pull-up current
VDD=3.6V, MR=0.0V
tRPFI
PFI rising threshold crossing to
PFO delay
tFPFI PFI falling threshold crossing to
PFO delay
ILEAK
Reset output leakage current
VOUT = VDD
IWDI
Watchdog input current
WDI pin = VDD = 3.6V
WDI pin = 0V, VDD = 3.6V
5
MIN MAX UNIT
450 A
0.7xVDD
0.7xVDD
0.8xVDD
0.6
0.6
0.3
0.3
0.3
V
V
V
V
V
V
V
0.7 1.8 s
140 280 ms
1.0 2.25 s
100 ns
3.0 3.15 V
20 mV
150 ns
100 ns
-20 -20 nA
0.576 0.624 V
-250 -25 A
20 s
40 s
1 A
20 A
-20 A

5 Page

UT01VS33D arduino
VDD
PFO_UND
Table 1. Under Voltage Over Voltage Truth Table
PFO_OV RESET_OD_UND RESET_OD_OV RESET_OD
Normal Operation
VDD < VDD_UND
VDD > VDD_OV
HIGH
LOW
HIGH
LOW
LOW
HIGH
HIGH
LOW
HIGH
Notes: -UND specifies under voltage case. -OV specifies overvoltage case
HIGH
HIGH
LOW
HIGH
LOW
LOW
uP or ASIC
Mode
Normal
Reset Asserted
Reset Asserted
11

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