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PDF PE43704 Data sheet ( Hoja de datos )

Número de pieza PE43704
Descripción RF Digital Step Attenuator
Fabricantes Peregrine Semiconductor 
Logotipo Peregrine Semiconductor Logotipo



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Product Description
The PE43704 is a HaRPtechnology-enhanced, high
linearity, 7-bit 50RF Digital Step Attenuator (DSA). It
offers maximum power handling of 28 dBm up to 8 GHz
and covers a 31.75 dB attenuation range in 0.25 dB,
0.5 dB, or 1.0 dB steps. The PE43704 is a pin-compatible
version of PE43703. It provides multiple CMOS control
interfaces and an optional VssEXT bypass mode to
improve spurious performance. It maintains high
attenuation accuracy over frequency and temperature and
exhibits very low insertion loss and low power
consumption. No blocking capacitors are required if DC
voltage is not present on the RF ports.
The PE43704 is manufactured on Peregrine’s
UltraCMOS® process, a patented variation of silicon-on-
insulator (SOI) technology on a sapphire substrate,
offering the performance of GaAs with the economy and
integration of conventional CMOS.
Figure 1. Package Type
32-lead 5x5 QFN
Figure 2. Functional Diagram
Product Specification
PE43704
UltraCMOS® RF Digital Step
Attenuator, 7-bit, 31.75 dB
with Optional VssEXT Bypass Mode
9 kHz - 8 GHz
Features
 HaRP™ technology enhanced
 Safe attenuation state transitions
 Attenuation options: covers a 31.75 dB
range in 0.25 dB, 0.5 dB, or 1.0 dB steps
 0.25 dB monotonicity for 6 GHz
 0.50 dB monotonicity for 7 GHz
 1.00 dB monotonicity for 8 GHz
 High power handling @ 8 GHz in 50
 28 dBm CW
 31 dBm instantaneous power
 High linearity
 IIP3 of 61 dBm
 1.8V/3.3V control logic
 Programming modes
 Direct parallel
 Latched parallel
 Serial
 Serial Addressable
 High-attenuation state @ power-up (PUP)
 ESD performance
 1.5kV HBM on all pins
DOC-02161
Document No. DOC-16514-6 | www.psemi.com
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
Page 1 of 20

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PE43704 pdf
PE43704
Product Specification
Figure 3. Pin Configuration (Top View)
Table 4. Pin Descriptions
Pin # Pin Name
Description
1 N/C No connect
2 VDD Supply voltage
3 P/S Serial/parallel mode select
4
5, 6,
8-17, 19
7
18
20
21
22
23
24
25
26
27
28
29
30
31
32
Pad
A0 Address bit A0 connection
GND Ground
RF11
RF21
VssEXT2
RF1 port (RF input)
RF2 port (RF output)
External Vss negative voltage control
A2 Address bit A2 connection
A1 Address bit A1 connection
LE Serial interface latch enable input
CLK
Serial interface clock input
SI Serial interface data input
C16 (D6)3
C8 (D5)3
C4 (D4)3
C2 (D3)3
C1 (D2)3
Parallel control bit, 16 dB
Parallel control bit, 8 dB
Parallel control bit, 4 dB
Parallel control bit, 2 dB
Parallel control bit, 1 dB
C0.5 (D1)3 Parallel control bit, 0.5 dB
C0.25 (D0)3 Parallel control bit, 0.25 dB
GND Exposed pad: ground for proper operation
Notes: 1. RF pins 7 and 18 must be at 0V DC. The RF pins do not require DC
blocking capacitors for proper operation if the 0V DC
requirement is met
2. Use VssEXT (pin 20) to bypass and disable internal
negative voltage generator. Connect VssEXT (pin 20) to GND (VssEXT = 0V)
to enable internal negative voltage generator
3. Ground C0.25, C0.5, C1 C2, C4, C8, C16 if not in use
Table 5. Operating Ranges
Parameter
Symbol Min Typ Max Unit
Supply voltage (normal
mode, VssEXT = 0V)1
VDD
2.3
Supply voltage (bypass
mode, VssEXT = -3.4V,
VDD3.4V for full spec.
VDD
2.7
compliance)2
Negative supply voltage
(bypass mode)2
VssEXT
-3.6
Supply current (normal
mode, VssEXT = 0V)1
Supply current (bypass
mode, VssEXT = -3.4V)2
Negative supply current
(bypass mode, VssEXT =
-3.4V)2
IDD
IDD
ISS
-40
Digital input high
VIH 1.17
Digital input low
VIL -0.3
Digital input current
ICTRL
RF input power, CW3
9 kHz < 50 MHz
50 MHz 8 GHz
PMAX,CW
RF input power, pulsed4
9 kHz < 50 MHz PMAX,PULSED
50 MHz 8 GHz
Operating temperature
range
TOP -40
5.5 V
3.4 5.5 V
-2.4 V
130 200 μA
50 80 μA
-16 μA
3.6 V
0.6 V
15 μA
see
Fig. 4 dBm
+28 dBm
see
Fig. 4 dBm
+31 dBm
25 +85 °C
Notes:
1. Normal mode: connect VssEXT (pin 20) to GND (VssEXT = 0V) to
enable internal negative voltage generator
2. Bypass mode: use VssEXT (pin 20) to bypass and disable internal
negative voltage generator
3. 100% duty cycle, all bands, 50
4. Pulsed, 5% duty cycle of 4620 µs period, 50
Document No. DOC-16514-6 | www.psemi.com
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
Page 5 of 20

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PE43704 arduino
PE43704
Product Specification
Typical Performance Data, 0.25 dB Step @ 25°C and VDD = 3.4V unless otherwise specified
Figure 7. 0.25 dB Step Attenuation vs. Frequency*
0.25
0.125
0.2GHz
0.9GHz
1.8GHz
0 2.2GHz
3GHz
0.125
4GHz
5GHz
6GHz
0.25
0 4 8 12 16 20 24 28 32
Attenuation Setting (dB)
* Monotonicity is held so long as step-attenuation does not cross below –0.25 dB
Figure 8. 0.25 dB Step, Actual vs. Frequency
35
30
25 0.9GHz
20 1.8GHz
2.2GHz
15
3GHz
10 4GHz
5 5GHz
6GHz
0
0 4 8 12 16 20 24 28 32
Ideal Attenuation (dB)
Figure 9. 0.25 dB Major State Bit Error vs.
Attenuation Setting
1.5
Figure 10. 0.25 dB Attenuation Error vs.
Frequency
1.5
1 0.25dB
0.5dB
1dB
0.5
2dB
4dB
0 8dB
16dB
0.5 31.75dB
0123456
Frequency (GHz)
1 0.2GHz
0.9GHz
1.8GHz
0.5 2.2GHz
3GHz
4GHz
0
5GHz
6GHz
0.5
0 4 8 12 16 20 24 28 32
Attenuation Setting (dB)
Document No. DOC-16514-6 | www.psemi.com
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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