PDF UT8R512K8 Data sheet ( Hoja de datos )

Número de pieza	UT8R512K8
Descripción	512K x 8 SRAM
Fabricantes	Aeroflex Circuit Technology
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No Preview Available ! Standard Products UT8R512K8 512K x 8 SRAM Data Sheet March 2009 www.aeroflex.com/memories FEATURES 15ns maximum access time Asynchronous operation for compatibility with industry- standard 512K x 8 SRAMs CMOS compatible inputs and output levels, three-state bidirectional data bus - I/O Voltage 3.3 volts, 1.8 volt core Operational environment: - Intrinsic total-dose: 300K rad(Si) - SEL Immune >100 MeV-cm2/mg - LETth (0.25): 53.0 MeV-cm2/mg - Memory Cell Saturated Cross Section 1.67E-7cm2/bit - Neutron Fluence: 3.0E14n/cm2 - Dose Rate - Upset 1.0E9 rad(Si)/sec - Latchup >1.0E11 rad(Si)/sec Packaging options: - 36-lead ceramic flatpack (3.762 grams) Standard Microcircuit Drawing 5962-03235 - QML Q & Vcompliant part INTRODUCTION The UT8R512K8 is a high-performance CMOS static RAM organized as 524,288 words by 8 bits. Easy memory expansion is provided by active LOW and HIGH chip enables (E1, E2), an active LOW output enable (G), and three-state drivers. This device has a power-down feature that reduces power consumption by more than 90% when deselected. Writing to the device is accomplished by taking chip enable one (E1) input LOW, chip enable two (E2) HIGH and write enable (W) input LOW. Data on the eight I/O pins (DQ0 through DQ7) is then written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking chip enable one (E1) and output enable (G) LOW while forcing write enable (W) and chip enable two (E2) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (DQ0 through DQ7) are placed in a high impedance state when the device is deselected (E1 HIGH or E2 LOW), the outputs are disabled (G HIGH), or during a write operation (E1 LOW, E2 HIGH and W LOW). A(18:0) E1 E2 G W INPUT DRIVER INPUT DRIVERS TOP/BOTTOM DECODER BLOCK DECODER INPUT DRIVERS ROW DECODER MEMORY ARRAY INPUT DRIVERS COLUMN DECODER COLUMN I/O DATA WRITE CIRCUIT INPUT DRIVERS CHIP ENABLE OUTPUT ENABLE DATA READ CIRCUIT OUTPUT DRIVERS WRITE ENABLE Figure 1. UT8R512K8 SRAM Block Diagram 1 DQ(7:0) 1 page DC ELECTRICAL CHARACTERISTICS (Pre and Post-Radiation)* Unless otherwise noted, Tc is per the temperature ordered SYMBOL PARAMETER CONDITION MIN MAX UNIT VIH High-level input voltage .7VDD2 V VIL Low-level input voltage .3VDD2 V VOL1 Low-level output voltage IOL = 8mA,VDD2 =VDD2 (min) .2VDD2 V VOH1 High-level output voltage IOH = -4mA,VDD2 =VDD2 (min) .8VDD2 V CIN1 Input capacitance ƒ = 1MHz @ 0V 12 pF CIO1 Bidirectional I/O capacitance ƒ = 1MHz @ 0V 12 pF IIN Input leakage current VIN = VDD2 and VSS IOZ Three-state output leakage VO = VDD2 and VSS, current VDD2 = VDD2 (max) G = VDD2 (max) -2 2 μA -2 2 μA IOS2, 3 Short-circuit output current VDD2 = VDD2 (max), VO = VDD2 VDD2 = VDD2 (max), VO = VSS -100 +100 mA IDD1(OP1) Supply current operating @ 1MHz Inputs : VIL = VSS + 0.2V VIH = VDD2 - 0.2V, IOUT = 0 VDD2 = VDD2 (max) VDD1 = 1.9V VDD1 = 2.0V 12 mA 19 mA IDD1(OP2) Supply current operating @66MHz Inputs : VIL = VSS + 0.2V, VIH = VDD2 - 0.2V, IOUT = 0 VDD2 = VDD2 (max) VDD1 = 1.9V VDD1 = 2.0V 30 mA 43 mA IDD2(OP1) Supply current operating @ 1MHz Inputs : VIL = VSS + 0.2V VIH = VDD2 - 0.2V, IOUT = 0 VDD1 = VDD1 (max) VDD2 = VDD2 (max) .2 mA IDD2(OP2) Supply current operating @66MHz Inputs : VIL = VSS + 0.2V, VIH = VDD2 - 0.2V, IOUT = 0 VDD1 = VDD1 (max), VDD2 = VDD2 (max) 4 mA 5 5 Page A(18:0) E1 tAVET tETEF E2 or tAVET tETEF E1 E2 W tWLEF D(7:0) Q(7:0) tWLQZ APPLIED DATA tDVEF tEFDX Assumptions & Notes: 1. G < VIL (max). (If G > VIH (min) then Q(7:0) will be in three-state for the entire cycle). 2. Either E1 scenario above can occur. tAVAV tEFAX tEFAX Figure 4b. SRAM Write Cycle 2: Chip Enable - Controlled Access 11 11 Page

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