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PDF UT54ACTS365 Data sheet ( Hoja de datos )
| Número de pieza | UT54ACTS365 | |
| Descripción | Hex Buffers/Line Drivers | |
| Fabricantes | Aeroflex Circuit Technology | |
| Logotipo |  |
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Standard Products
UT54ACS365/UT54ACTS365
Hex Buffers/Line Drivers with Three-State Outputs
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
1.2μ CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 16-pin DIP
- 16-lead flatpack
UT54ACS365- SMD 5962-96586
UT54ACTS365 - SMD 5962-96587
DESCRIPTION
The UT54ACS365 and UT54ACTS365 are non-inverting hex
buffer and line driver with three-state outputs. The output en-
ables (OE1 and OE2) control the three-state outputs. If OE1 or
OE2 is high, the outputs will be in a high impedance state. For
data, both OE1 and OE2 must be low.
The devices are characterized over full military temperature
range of -55°C to +125°C.
FUNCTION TABLE
OE1
L
L
X
H
INPUTS
OE2
L
L
H
X
OUTPUT
AY
LL
HH
XZ
XZ
LOGIC SYMBOL
(1)
OE1
(15)
OE2
&
EN
PINOUTS
OE1
A1
Y1
A2
Y2
A3
Y3
VSS
(2)
A1
(4)
A2
(6)
A3
(10)
A4
(12)
A5
A6 (14)
(3)
Y1
(5)
Y2
(7)
Y3
(9)
Y4
(11)
Y5
(13) Y6
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
1
16-Pin DIP
Top View
OE1 1 16 VDD
A1 2 15 OE2
Y1 3 14 A6
A2 4 13 Y6
Y2 5 12 A5
A3 6 11 Y5
Y3 7 10 A4
VSS 8
9 Y4
16-Lead Flatpack
Top View
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
VDD
OE2
A6
Y6
A5
Y5
A4
Y4
1 page  
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, -
50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to VIH(min) and VIL(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density ≤ 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765
pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose ≤ 1E6 rads(Si).
8. Power does not include power contribution of any TTL output sink current.
9. Power dissipation specified per switching output.
10. This value is guaranteed based on characterization data, but not tested.
5
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| PDF Descargar | [ Datasheet UT54ACTS365.PDF ] | |
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