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PDF GD25D05B Data sheet ( Hoja de datos )

Número de pieza GD25D05B
Descripción Uniform sector dual and quad serial flash
Fabricantes ELM 
Logotipo ELM Logotipo



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No Preview Available ! GD25D05B Hoja de datos, Descripción, Manual

http://www.elm-tech.com
GD25D05B
DATASHEET

1 page




GD25D05B pdf
GD25D05BxIGx Uniform sector dual and quad serial flash
2. GENERAL DESCRIPTION
http://www.elm-tech.com
The GD25D05B (512K-bit) serial flash supports the standard serial peripheral interface (SPI), and supports
the Dual Output: Serial Clock, Chip Select, Serial Data I/O0 (SI), O1 (SO). The Dual Output data is transferred
with speed of 160Mbits/s.
Connection Diagram
8-LEAD SOP
PIN Description
Pin Name
CS#
SO (O1)
WP#
VSS
SI (IO0)
SCLK
NC
VCC
I/O
I
O
I
I/O
I
8-LEAD USON
Description
Chip Select Input
Data Output ( Data Output 1 )
Write Protect Input
Ground
Data Input ( Data Input Output 0 )
Serial Clock Input
No Connection
Power Supply
Block Diagram
WP#
Write Control
Logic
SCLK
CS#
SI(IO0)
SO(O1)
SPI
Command &
Control Logic
Status
Register
High Voltage
Generators
Flash
Memory
Page Address
Latch/Counter
Column Decode And
256-Byte Page Buffer
Byte Address
Latch/Counter
28 - 5
Rev.1.0

5 Page





GD25D05B arduino
GD25D05BxIGx Uniform sector dual and quad serial flash
http://www.elm-tech.com
Figure 3. Read Status Register Sequence Diagram
CS#
SCLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Command
SI
05H
SO
High-Z
S7~S0 out
S7~S0 out
76543210765432107
MSB
MSB
7.4. Write Status Register (WRSR) (01H)
The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. A Write
Enable (WREN) instruction must be executed previously to set the Write Enable Latch (WEL) bit, before it can
be accepted.
The Write Status Register (WRSR) instruction is entered by driving Chip Select (CS#) Low, followed by the
instruction code and the data byte on Serial Data Input (DI).
The Write Status Register (WRSR) instruction has no effect on S6, S5, S1 and S0 of the Status Register. S6
and S5 are always read as 0. Chip Select (CS#) must be driven High after the eighth bit of the data byte has been
latched in. Otherwise, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select (CS#)
is driven High, the self-timed Write Status Register cycle (the duration is tw) is initiated. While the Write Status
Register cycle is in progress, reading Status Register to check the Write in Progress (WIP) bit is achievable.
The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and turn to 0 on the
completion of the Write Status Register. When the cycle is completed, the Write Enable Latch (WEL) is reset to 0.
The Write Status Register (WRSR) instruction allows the user to change the values of the Block Protect (BP2,
BP1, BP0) bits, which are utilized to define the size of the read-only area.
The Write Status Register (WRSR) instruction also allows the user to set or reset the Status Register Protect
(SRP) bit in accordance with the Write Protect (WP#) signal, by setting which the device can enter into
Hardware Protected Mode (HPM). The Write Status Register (WRSR) instruction is not executed once enter
into the Hardware Protected Mode (HPM).
Figure 4. Write Status Register Sequence Diagram
CS#
SCLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Command
Status Register in
SI 01H 7 6 5 4 3 2 1 0
SO
MSB
High-Z
28 - 11
Rev.1.0

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