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PDF GS1582 Data sheet ( Hoja de datos )
| Número de pieza | GS1582 | |
| Descripción | Multi-Rate Serializer | |
| Fabricantes | Gennum | |
| Logotipo |  |
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GS1582 Multi-Rate Serializer with Cable Driver, Audio Multiplexer and
ClockCleanerTM
Key Features
• HD-SDI, SD-SDI, DVB-ASI transmitter with audio
embedding
• Integrated SMPTE 292M and 259M-C compliant cable
driver
• Integrated ClockCleaner™
• User selectable video processing features, including:
Generic ancillary data insertion
Support for HVF or EIA/CEA-861 timing input
Automatic standard detection and indication
Enhanced SMPTE 352M payload identifier
generation and insertion
TRS, CRC, ANC data checksum, and line number
calculation and insertion
EDH packet generation and insertion
Illegal code remapping
SMPTE 292M and SMPTE 259M-C compliant
scrambling and NRZ → NRZI encoding
Blanking of input HANC and VANC space
• User selectable audio processing features, including:
SMPTE 299M and SMPTE 272M-A/C compliant
audio embedding
Support for up to 8 channels
Support for audio group replacement
• JTAG test interface
• 1.8V core and 3.3V charge pump power supply
• 1.8V and 3.3V digital I/O support
• Low power standby mode
• Operating temperature range: -20oC to +85oC
• Pb-free, RoHS compliant, 11mm x 11mm 100-ball BGA
package
Applications
• SMPTE 292M and SMPTE 259M-C Serial Digital
Interfaces
• DVB-ASI Serial Digital Interfaces
Description
The GS1582 is the next generation multi-standard
serializer with an integrated cable driver. The device
provides robust parallel to serial conversion, generating a
SMPTE 292M/259M-C compliant serial digital output
signal. The integrated cable driver features an output
disable (high impedance) mode and an adjustable signal
swing. Data input is accepted in 20-bit parallel format or
10-bit parallel format. An associated parallel clock input
must be provided at the appropriate operating frequency;
74.25/74.1758/13.5MHz (20-bit mode) or
148.5/148.352/27MHz (10-bit mode).
The GS1582 features an internal PLL which, if desired, can
be configured for a loop bandwidth below 100kHz. When
used in conjunction with the GO1555 Voltage Controlled
Oscillator, the GS1582 can tolerate well in excess of 300ps
jitter on the input PCLK and still provide output jitter within
SMPTE specifications.
In addition to serializing the input, the GS1582 performs
NRZ-to-NRZI encoding and scrambling as per SMPTE
292M/259M-C when operating in SMPTE mode. When
operating in DVB-ASI mode, the device will insert K28.5
sync characters and 8b/10b encode the data prior to
serialization. The device also provides a range of other data
processing functions. All processing features are optional
and may be enabled/disabled via external control pin(s)
and/or host interface programming.
The GS1582 can embed up to 8 channels of audio into the
video data stream in accordance with SMPTE 299M and
SMPTE 272M. The audio input signal formats supported by
the device include AES/EBU and I2S serial digital formats
with a 16, 20 or 24 bit sample size and a 48 kHz sample rate.
Additional audio processing features include individual
channel enable, channel swap, group swap, ECC
generation and audio channel status insertion.
Typical power consumption, including the GO1555 VCO, is
500mW. The standby feature allows the power to be
reduced to 125mW. Power may be reduced to less than
GS1582 Multi-Rate Serializer with Cable Driver, Audio Multiplexer and ClockCleanerTM
www.gennum.com
Data Sheet
40117 - 4
December 2011
1 of 115
1 page  
4.7.19 Audio Crosspoint............................................................................................................. 58
4.7.20 Audio Word Clock .......................................................................................................... 59
4.7.21 GS1582 SD Audio FIFO Block ..................................................................................... 59
4.7.22 Audio Sample Distributions......................................................................................... 60
4.7.23 Audio Mute........................................................................................................................ 63
4.8 Ancillary Data Insertion .............................................................................................................. 63
4.8.1 Ancillary Data Insertion Operating Mode................................................................. 64
4.8.2 HANC Insertion.................................................................................................................. 65
4.8.3 VANC Insertion .................................................................................................................. 66
4.9 Additional Processing Functions .............................................................................................. 66
4.9.1 ANC Data Blanking ........................................................................................................... 66
4.9.2 Automatic Video Standard Detection......................................................................... 66
4.9.3 Video Standard Indication ............................................................................................. 67
4.9.4 Packet Generation and Insertion.................................................................................. 69
4.10 Parallel to Serial Conversion ................................................................................................... 74
4.11 Internal ClockCleanerTM PLL .................................................................................................. 75
4.11.1 External VCO.................................................................................................................... 75
4.11.2 Loop Filter.......................................................................................................................... 75
4.11.3 Lock Detect Output......................................................................................................... 76
4.12 Serial Digital Output .................................................................................................................. 77
4.12.1 Output Swing.................................................................................................................... 77
4.13 GSPI Host Interface ..................................................................................................................... 77
4.13.1 Command Word Description ...................................................................................... 79
4.13.2 Data Read and Write Timing ....................................................................................... 79
4.13.3 Configuration and Status Registers........................................................................... 81
4.14 JTAG Test Operation ................................................................................................................ 106
4.15 Device Reset ................................................................................................................................ 108
5. Application Reference Design ............................................................................................................. 109
5.1 Typical Application Circuit (Part A) ....................................................................................... 109
5.2 Typical Application Circuit (Part B) ....................................................................................... 110
6. References & Relevant Standards ....................................................................................................... 111
7. Package & Ordering Information ........................................................................................................ 112
7.1 Package Dimensions ................................................................................................................... 112
7.2 Packaging Data ............................................................................................................................. 113
7.3 Marking Diagram ......................................................................................................................... 113
7.4 Solder Reflow Profile .................................................................................................................. 114
7.5 Ordering Information ................................................................................................................. 114
GS1582 Multi-Rate Serializer with Cable Driver, Audio
Multiplexer and ClockCleanerTM
Data Sheet
40117 - 4
December 2011
5 of 115
5 Page 
Table 1-1: Pin Descriptions (Continued)
Pin
Number
A3
A4
A5, E1, G10,
K8
A6, B6
A7
A8
A9
A10
Name
F/DE
H/HSYNC
CORE_VDD
PD_VDD
LF
VCO_VCC
VCO
CP_VDD
Timing
Type Description
Synchronous
with PCLK
Synchronous
with PCLK
Non
Synchronous
Analog
Analog
Analog
Analog
Analog
Input
PARALLEL DATA TIMING
Signal levels are LVCMOS/LVTTL compatible.
TIM_861 = LOW:
Used to indicate the ODD / EVEN field of the video signal when
DETECT_TRS is set LOW. The device will set the F bit in all outgoing
TRS signals for the entire period that the F input signal is HIGH
(IOPROC_EN/DIS must also be HIGH).
The F signal should be set HIGH for the entire period of field 2 and
should be set LOW for all lines in field 1 and for all lines in
progressive scan systems.
The F signal is ignored when DETECT_TRS = HIGH.
TIM_861 = HIGH:
The DE signal is used to indicate the active video period. DE is HIGH
for active data and LOW for blanking. See Section 4.3.1 and
Section 4.3.2 for timing details.
The DE signal is ignored when DETECT_TRS = HIGH.
Input
PARALLEL DATA TIMING
Signal levels are LVCMOS/LVTTL compatible.
TIM_861 = LOW:
The H signal is used to indicate the portion of the video line
containing active video data, when DETECT_TRS is set low.
Active Line Blanking
The H signal should be set HIGH for the entire horizontal blanking
period, including the EAV and SAV TRS words, and LOW otherwise.
This is the default setting.
TRS Based Blanking (H_CONFIG = 1h)
The H signal should be set HIGH for the entire horizontal blanking
period as indicated by the H bit in the received TRS ID words, and
LOW otherwise.
The H signal is ignored when DETECT_TRS = HIGH.
TIM_861 = HIGH:
The HSYNC signal indicates horizontal timing. See Section 4.3.1 for
timing details.
The HSYNC signal is ignored when DETECT_TRS = HIGH.
Input Power supply connection for the digital core logic. Connect to +1.8V
Power DC digital.
Input Power supply connection for the phase detector. Connect to +1.8V
Power DC analog.
Input PLL loop filter connection.
Output Power supply for the external voltage controlled oscillator.
Power 2.5V DC supplied by the device to the external VCO.
Input Input from external VCO.
Input Power supply connection for the charge pump and on chip VCO
Power regulator. Connect to +3.3V DC analog.
GS1582 Multi-Rate Serializer with Cable Driver, Audio
Multiplexer and ClockCleanerTM
Data Sheet
40117 - 4
December 2011
11 of 115
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet GS1582.PDF ] | |
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