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PDF GS1670 Data sheet ( Hoja de datos )
| Número de pieza | GS1670 | |
| Descripción | HD/SD SDI Receiver Complete | |
| Fabricantes | Semtech | |
| Logotipo |  |
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GS1670
HD/SD SDI Receiver Complete with SMPTE Audio and Video Processing
Key Features
• Operation at 1.485Gb/s, 1.485/1.001Gb/s and 270Mb/s
• Supports SMPTE 292, SMPTE 259M-C and DVB-ASI
• Integrated Reclocker with low phase noise, integrated
VCO
• Serial digital reclocked, or non-reclocked loop-through
output
• Integrated audio de-embedder for 8 channels of 48kHz
audio
• Integrated audio clock generator
• Ancillary data extraction
• Parallel data bus selectable as either 20-bit or 10-bit
• Comprehensive error detection and correction
features
• Output H, V, F or CEA 861 timing signals
• 1.2V digital core power supply, 1.2V and 3.3V analog
power supplies, and selectable 1.8V or 3.3V I/O power
supply
• GSPI host interface
• -20ºC to +85ºC operating temperature range
• Low power operation (typically 300mW)
• Small 11mm x 11mm 100-ball BGA package
• Pb-free and RoHS compliant
Errata
Refer to Errata document entitled GS1670/GS1671 Errata
for this device (document number 53878).
Applications
HD-SDI
Application: 1080p30 or 720p60 Monitor
EQ
(GS1574A
or GS2984)
AES - OUT
GS1670
AUDIO 1/2
AUDIO 3/4
AUDIO 5/6
AUDIO 7/8
Audio Clocks
Audio
Selector
20-bit
HV F/PCLK
Video
Processor
C TR L/TIMECODE
DAC
Speakers
DAC
Display
Application: Multi-format Downconverter
SD/HD-SDI
EQ
(GS1574A or
GS2984)
GS1670
20-bit
HV F /P CLK
10-bit SD Bypass
Memory
Video
Downconverter&
Aspect Ratio
Conversion
20-bit
HD/SD
Serializer
(GS1672)
HD/SD-SDI
Analog
Sync
Sync
Seperator
GS4901
AES 1/2
AES 3/4
AES 5/6
AES 7/8
Audio Clocks
HV F / P CLK
Audio
Processing &
Delay
AES 1/2
AES 3/4
AES 5/6
AES 7/8
Application: Multi-input Video Monitoring System
HD-SDI
Input 1
EQ
(GS1574A
or GS2984)
HD-SDI
Input 2
EQ
(GS1574A
or GS2984)
GS1670
20-bit
HV F / P CLK
GS1670
20-bit
HV F / P CLK
Video
Memory
Video
Formatter
HV /DE /P CLK
DVI/
VGA DAC
Video
Output
HD-SDI
Input n
EQ
(GS1574A
or GS2984)
Analog
Sync
Sync
Seperator
GS1670
20-bit
HV F / P CLK
AES BUS
GS4911
Audio
Select
HV F /P CLK
Audio Clocks
On Screen
Display
Generator
Audio
Processor
AE S OUT 1/2
AE S OUT 3/4
AE S OUT 5/6
AE S OUT 7/8
GS1670 HD/SD SDI Receiver
Data Sheet
53831 - 2
September 2012
www.semtech.com
1 of 126
1 page  
4.15 Video Signal Error Detection & Indication ......................................................................... 50
4.15.1 TRS Error Detection........................................................................................................ 52
4.15.2 Line Based CRC Error Detection ................................................................................ 52
4.15.3 EDH CRC Error Detection............................................................................................. 53
4.15.4 HD Line Number Error Detection .............................................................................. 53
4.16 Ancillary Data Detection & Indication ................................................................................. 53
4.16.1 Programmable Ancillary Data Detection................................................................ 54
4.16.2 SMPTE 352M Payload Identifier ................................................................................ 55
4.16.3 Ancillary Data Checksum Error ................................................................................. 55
4.16.4 Video Standard Error..................................................................................................... 56
4.17 Signal Processing ......................................................................................................................... 56
4.17.1 TRS Correction & Insertion........................................................................................... 57
4.17.2 Line Based CRC Correction & Insertion ................................................................... 58
4.17.3 Line Number Error Correction & Insertion ............................................................. 58
4.17.4 ANC Data Checksum Error Correction & Insertion ............................................. 58
4.17.5 EDH CRC Correction & Insertion ............................................................................... 58
4.17.6 Illegal Word Re-mapping ............................................................................................. 59
4.17.7 TRS and Ancillary Data Preamble Remapping...................................................... 59
4.17.8 Ancillary Data Extraction............................................................................................. 59
4.18 Audio De-embedder ................................................................................................................... 63
4.18.1 Serial Audio Data I/O Signals...................................................................................... 63
4.18.2 Serial Audio Data Format Support ............................................................................ 64
4.18.3 Audio Processing............................................................................................................. 69
4.18.4 Error Reporting ................................................................................................................ 75
4.19 GSPI - HOST Interface ................................................................................................................ 76
4.19.1 Command Word Description ...................................................................................... 76
4.19.2 Data Read or Write Access........................................................................................... 77
4.19.3 GSPI Timing....................................................................................................................... 78
4.20 Host Interface Register Maps .................................................................................................. 80
4.20.1 Video Core Registers...................................................................................................... 80
4.20.2 SD Audio Core Registers............................................................................................... 89
4.20.3 HD Audio Core Registers............................................................................................ 103
4.21 JTAG Test Operation ................................................................................................................ 119
4.22 Device Power-up ....................................................................................................................... 120
4.23 Device Reset ................................................................................................................................ 120
4.24 Standby Mode ............................................................................................................................ 120
5. Application Reference Design ............................................................................................................. 121
5.1 Typical Application Circuit ......................................................................................................121
6. References & Relevant Standards ....................................................................................................... 122
7. Package & Ordering Information ........................................................................................................ 123
7.1 Package Dimensions ................................................................................................................... 123
7.2 Packaging Data ............................................................................................................................. 124
7.3 Marking Diagram ......................................................................................................................... 124
7.4 Solder Reflow Profiles ................................................................................................................ 125
7.5 Ordering Information ................................................................................................................. 125
GS1670 HD/SD SDI Receiver
Data Sheet
53831 - 2
September 2012
5 of 126
5 Page 
Table 1-1:Pin Descriptions (Continued)
Pin
Number
D4, E4, F4
D5, E5, F5,
G5
D6, E6, F6,
G6
D7
D8
E1
E2
E7
E8
F1
Name
Timing
Type
Description
PLL_GND
CORE_GND
CORE_VDD
SW_EN
JTAG/HOST
SDI_VDD
SDI_GND
SDOUT_TDO
SDIN_TDI
TERM
Input Power
Input Power
GND pins for the Reclocker PLL. Connect to analog GND.
GND connection for device core. Connect to digital GND.
Input Power POWER connection for device core. Connect to 1.2V DC digital.
Input
Input
Input Power
Input Power
Output
Input
Analog Input
CONTROL SIGNAL INPUT
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Used to enable switch-line locking, as described in Section 4.9.1.
CONTROL SIGNAL INPUT
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Used to select JTAG test mode or host interface mode.
When JTAG/HOST is HIGH, the host interface port is configured for
JTAG test.
When JTAG/HOST is LOW, normal operation of the host interface
port resumes.
POWER pin for SDI buffer. Connect to 3.3V DC analog.
GND pin for SDI buffer. Connect to analog GND.
COMMUNICATION SIGNAL OUTPUT
Please refer to the Output Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
GSPI serial data output/test data out.
In JTAG mode (JTAG/HOST = HIGH), this pin is used to shift test
results from the device.
In host interface mode, this pin is used to read status and
configuration data from the device.
Note: GSPI is slightly different than the SPI. For more details on GSPI,
please refer to 4.19 GSPI - HOST Interface.
COMMUNICATION SIGNAL INPUT
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
GSPI serial data in/test data in.
In JTAG mode (JTAG/HOST = HIGH), this pin is used to shift test data
into the device.
In host interface mode, this pin is used to write address and
configuration data words into the device.
Decoupling for internal SDI termination resistors.
GS1670 HD/SD SDI Receiver
Data Sheet
53831 - 2
September 2012
11 of 126
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet GS1670.PDF ] | |
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