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PDF GS4900B Data sheet ( Hoja de datos )

Número de pieza GS4900B
Descripción SD Clock and Timing Generator
Fabricantes Gennum 
Logotipo Gennum Logotipo



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GS4901B/GS4900B SD Clock and Timing Generator with GENLOCK
Key Features
Video Clock Synthesis
• Pre-programmed for 4 video clock periods (14.32 MHz, 27
MHz, 36 MHz, and 54 MHz)
• Accuracy of free-running clock frequency limited only by
crystal reference
• One differential and two single-ended video clock outputs
• Each clock may be individually delayed for skew control
• Video output clock may be directly connected to Gennum’s
serializers for a SMPTE-compliant SDI output
Audio Clock Synthesis (GS4901B only)
• Three audio clock outputs
• Generates any audio clock up to 512*96kHz
• Pre-programmed for 7 audio clocks
Timing Generation
• Generates up to 8 timing signals at a time
• Choose from 9 pre-programmed timing signals: H and V sync
and blanking, F Sync, F Digital, AFS (GS4901B only), Display
Enable, 10FID, and up to 4 user-defined timing signals
• Pre-programmed to generate timing for 9 different video
formats
Genlock Capability
• Clocks may be free-running or genlocked to an input
reference with a variable offset step size of 100-200ps
(depending on exact clock frequency)
• Variable timing offset step size of 100-200ps up to one frame
• Output may be cross-locked to a different input reference
• Freeze operation on loss of reference
• Optional crash or drift lock on application of reference
• Automatic input format detection
General Features
• Reduces design complexity and saves board space - 9mm x
9mm package plus crystal reference replaces multiple
VCXOs, PLLs and timing generators
• Pb-free and RoHS Compliant
• Low power operation typically 300mW
• 1.8V core and 1.8V or 3.3V I/O power supplies
• 64-PIN QFN package
Applications
• Video cameras; Digital audio and/or video recording/play
back devices; Digital audio and/or video processing devices;
Computer/video displays; DVD/MPEG devices; Digital Set
top boxes; Video projectors; High definition video systems;
Multi-media PC applications
Description
The GS4901B is a highly flexible, digitally controlled clock
synthesis circuit and timing generator with genlock
capability. It can be used to generate video and audio
clocks and timing signals, and allows multiple devices to be
genlocked to an input reference.
The GS4900B includes all the features of the GS4901B, but
does not offer audio clocks or AFS pulse generation.
The GS4901B/GS4900B will recognize input reference
signals conforming to 36 different video standards, and will
genlock the output timing information to the incoming
reference. The GS4901B/GS4900B supports cross-locking,
allowing the output to be genlocked to an incoming
reference that is different from the output video standard
selected.
The user may select to output one of 4 different video
sample clock rates. The chosen clock frequency can be
further divided using internal dividers, and is available on
two video clock outputs and one LVDS video clock output
pair. The video clocks are frequency and phased-locked to
the horizontal timing reference, and can be individually
delayed with respect to the timing outputs for clock skew
control.
Eight user-selectable timing outputs are provided that can
automatically produce the following timing signals for 9
different video formats: HSync, Hblanking, VSync,
Vblanking, F sync, F digital, AFS (GS4901B only), DE, and
10FID. These timing outputs may be locked to the input
reference signal for genlock timing and may be phase
adjusted via internal registers.
In addition, the GS4901B provides three audio sample
clock outputs that can produce audio clocks up to 512fs
with fs ranging from 9.7kHz to 96kHz. Audio to video
phasing is accomplished by an external 10FID input
reference, a 10FID signal specified via internal registers, or
a user-programmed audio frame sequence.
The GS4901B/GS4900B is Pb-free, and the encapsulation
compound does not contain halogenated flame retardant
(RoHS Compliant).
GS4901B/GS4900B SD Clock and Timing Generator
with GENLOCK
Data Sheet
37703 - 4
December 2009
www.gennum.com
1 of 102

1 page




GS4900B pdf
3.10 GSPI Host Interface ..................................................................................................................... 64
3.10.1 Command Word Description ...................................................................................... 66
3.10.2 Data Read and Write Timing ....................................................................................... 66
3.10.3 Configuration and Status Registers........................................................................... 67
3.11 JTAG ................................................................................................................................................. 93
3.12 Device Power-Up ........................................................................................................................ 94
3.12.1 Power Supply Sequencing ........................................................................................... 94
3.13 Device Reset .................................................................................................................................. 94
4. Application Reference Design ............................................................................................................... 95
4.1 GS4901B Typical Application Circuit ..................................................................................... 95
4.2 GS4900B Typical Application Circuit ..................................................................................... 96
5. References & Relevant Standards ......................................................................................................... 97
6. Package & Ordering Information .......................................................................................................... 98
6.1 Package Dimensions ..................................................................................................................... 98
6.2 Recommended PCB Footprint ................................................................................................... 99
6.3 Packaging Data ............................................................................................................................... 99
6.4 Ordering Information ................................................................................................................. 100
7. Revision History........................................................................................................................................ 101
List of Figures
GS4901B Functional Block Diagram ......................................................................................................... 2
GS4900B Functional Block Diagram ......................................................................................................... 3
Figure 1-1: XTAL1 and XTAL2 Reference Circuits .............................................................................. 18
Figure 2-1: PCLK to TIMING_OUT Signal Output Timing ................................................................. 32
Figure 2-2: Maximum Pb-free Solder Reflow Profile (preferred) .................................................. 34
Figure 2-3: Standard Pb Solder Reflow Profile .................................................................................... 34
Figure 3-1: SD-HD Calculation .................................................................................................................. 38
Figure 3-2: Output Accuracy and Modes of Operation ..................................................................... 40
Figure 3-3: Example HSYNC, VSYNC, and FSYNC Analog Input Timing from a
Sync Separator ................................................................................................................................................ 41
Figure 3-4: Example H Blanking, V Blanking, and F Digital Input Timing from an
SDI Deserializer .............................................................................................................................................. 41
Figure 3-5: 10FID Input Timing ................................................................................................................. 42
Figure 3-6: Default 10FID Output Timing .............................................................................................. 58
Figure 3-7: Optional 10FID Output Timing ........................................................................................... 59
Figure 3-8: AFS Output Timing ................................................................................................................. 60
Figure 3-9: USER Programmable Output Signal .................................................................................. 61
Figure 3-10: Audio Clock Block Diagram for HD Demux Operation ........................................... 64
Figure 3-11: GSPI Application Interface Connection ........................................................................ 65
Figure 3-12: Command Word Format ..................................................................................................... 66
Figure 3-13: Data Word Format ................................................................................................................ 66
Figure 3-14: GSPI Read Mode Timing ..................................................................................................... 67
Figure 3-15: GSPI Write Mode Timing .................................................................................................... 67
Figure 3-16: In-Circuit JTAG ...................................................................................................................... 93
Figure 3-17: System JTAG ........................................................................................................................... 94
GS4901B/GS4900B SD Clock and Timing Generator
with GENLOCK
Data Sheet
37703 - 4
December 2009
5 of 102

5 Page





GS4900B arduino
Table 1-1: Pin Descriptions (Continued)
Pin
Number
17
Name
VSYNC
18, 31, 38, IO_VDD
50, 62
19 FSYNC
27, 25, 24, VID_STD[5:0]
23, 22, 21
26, 44
CORE_VDD
Timing
Type Description
Non Input
Synchronous
– Power
Supply
Non Input
Synchronous
Non Input
Synchronous
– Power
Supply
REFERENCE SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
The VSYNC external reference signal is applied to this pin by the
application layer. When the GS4901B/GS4900B is operating in
Genlock mode, the device senses the polarity of the VSYNC input
automatically, and references to the leading edge.
This signal must adhere to one of the 36 defined video standards
supported by the device. In this mode of operation, the VSYNC
input provides a vertical scanning reference signal.
The VSYNC signal may have analog timing, such as from a sync
separator, or may be digital such as from an SDI deserializer.
Section 1.4 on page 19 describes the 36 video formats recognized by
the GS4901B/GS4900B.
Most positive power supply connection for the digital I/O signals.
Connect to either +1.8V DC or +3.3V DC.
NOTE: All five IO_VDD pins must be powered by the same voltage.
REFERENCE SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
The FSYNC external reference signal is applied to this pin by the
application layer.
The first field is defined as the field in which the first broad pulse
(also known as serration) is in the first half of a line. The FSYNC
signal should be set HIGH during the first field for sync-based
references.
Then this signal must adhere to one of the 36 defined video
standards supported by the device. In this mode of operation, the
FSYNC input provides an odd/even field input reference.
The FSYNC signal may have analog timing, such as from a sync
separator, or may be digital such as from an SDI deserializer.
Section 1.4 on page 19 describes the 36 video formats recognized by
the GS4901B/GS4900B.
For blanking-based references, the FSYNC signal should be set HIGH
during the second field.
NOTE: If the input reference format does not include an F sync
signal, this pin should be held LOW.
CONTROL SIGNAL INPUTS
Signal levels are LVCMOS/LVTTL compatible.
Video Standard Select.
Used to select the desired video format for video clock and timing
signal generation.
4 different video sample clocks, as well as 9 different video format
timing signal outputs may be selected using these pins.
NOTE: The VID_STD[5:4] pins should be grounded by the application
layer since these pins are not required to select output video
standards 1 to 10.
For details on the supported video standards and video clock
frequency selection, please see Section 1.4 on page 19.
Most positive power supply connection for the digital core. Connect
to +1.8V DC.
GS4901B/GS4900B SD Clock and Timing Generator
with GENLOCK
Data Sheet
37703 - 4
December 2009
11 of 102

11 Page







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