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PDF UT54ACS244 Data sheet ( Hoja de datos )

Número de pieza UT54ACS244
Descripción Octal Buffers & Line Drivers
Fabricantes Aeroflex Circuit Technology 
Logotipo Aeroflex Circuit Technology Logotipo



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No Preview Available ! UT54ACS244 Hoja de datos, Descripción, Manual

Standard Products
UT54ACS244/UT54ACTS244
Octal Buffers & Line Drivers, Three-State Outputs
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
‰ Three-state outputs drive bus lines or buffer memory address
registers
‰ 1.2μ CMOS
- Latchup immune
‰ High speed
‰ Low power consumption
‰ Single 5 volt supply
‰ Available QML Q or V processes
‰ Flexible package
- 20-pin DIP
- 20-lead flatpack
‰ UT54ACS244 - SMD 5962-96570
‰ UT54ACTS244 - SMD 5962-96571
PINOUTS
DESCRIPTION
The UT54ACS244 and the UT54ACTS244 are non-inverting
octal buffer and line drivers which improve the performance and
density of three-state memory address drivers, clock drivers, and
bus-oriented receivers and transmitters.
The devices are characterized over full military temperature
range of -55°C to +125°C.
FUNCTION TABLE
INPUTS
1G, 2G
L
L
H
A
L
H
X
OUTPUT
Y
L
H
Z
LOGIC SYMBOL
1G (1)
(2)
1A1
1A2 (4)
(6)
1A3
(8)
1A4
EN
(18)
1Y1
(16)
1Y2
(14)
1Y3
(12)
1Y4
1G
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
VSS
(19)
2G
EN
(11)
2A1
(13)
2A2
(15)
2A3
(17)
2A4
(9)
2Y1
(7)
2Y2
(5)
2Y3
(3)
2Y4
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC
Publication 617-12.
1
20-Pin DIP
Top View
1G 1 20 VDD
1A1 2 19 2G
2Y4 3 18 1Y1
1A2 4 17 2A4
2Y3 5 16 1Y2
1A3 6 15 2A3
2Y2 7 14 1Y3
1A4 8 13 2A2
2Y1 9 12 1Y4
VSS 10 11 2A1
20-Lead Flatpack
Top View
1 20
2 19
3 18
4 17
5 16
6 15
7 14
8 13
9 12
10 11
VDD
2G
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1

1 page




UT54ACS244 pdf
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, -
50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to VIH(min) and VIL(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765
pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose 1E6 rads(Si).
8. Power does not include power contribution of any TTL output sink current.
9. Power dissipation specified per switching output.
10. This value is guaranteed based on characterization data, but not tested.
5

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