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PDF UT54ACTS190 Data sheet ( Hoja de datos )

Número de pieza UT54ACTS190
Descripción Synchronous 4-Bit Up-Down BCD Counters
Fabricantes Aeroflex Circuit Technology 
Logotipo Aeroflex Circuit Technology Logotipo



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No Preview Available ! UT54ACTS190 Hoja de datos, Descripción, Manual

Standard Products
UT54ACS190/UT54ACTS190
Synchronous 4-Bit Up-Down BCD Counters
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
‰ Single down/up count control line
‰ Look-ahead circuitry enhances speed of cascaded counters
‰ Fully synchronous in count modes
‰ Asynchronously presettable with load control
‰ 1.2μ CMOS
- Latchup immune
‰ High speed
‰ Low power consumption
‰ Single 5 volt supply
‰ Available QML Q or V processes
‰ Flexible package
- 16-pin DIP
- 16-lead flatpack
‰ UT54ACS190 - SMD 5962-96562
‰ UT54ACTS190 - SMD 5962-96563
DESCRIPTION
The UT54ACS190 and the UT54ACTS190 are synchronous 4-
bit reversible up-down BCD decade counters. Synchronous
counting operation is provided by having all flip-flops clocked
simultaneously so that the outputs change coincident with each
other when so instructed. Synchronous operation eliminates the
output counting spikes associated with asynchronous counters.
The outputs of the four flip-flops are triggered on a low-to-high-
level transition of the clock input if the enable input (CTEN) is
low. A logic one applied to CTEN inhibits counting. The di-
rection of the count is determined by the level of the down/up
(D/U) input. When D/U is low, the counter counts up and when
D/U is high, it counts down.
The counters feature a fully independent clock circuit. Changes
at control inputs (CTEN and D/U) that will modify the operating
mode have no effect on the contents of the counter until clocking
occurs.
The counters are fully programmable. The outputs may be preset
to either logic level by placing a low on the load input and en-
tering the desired data at the data inputs. The output will change
to agree with the data inputs independently of the level of the
clock input. The asynchronous load allows counters to be used
as modulo-N dividers by simply modifying the count length with
the preset inputs.
If preset to an illegal state, the counter returns to a normal se-
quence in one or two counts.
PINOUTS
16-Pin DIP
Top View
B 1 16 VDD
QB 2 15 A
QA 3 14 CLK
CTEN 4 13 RCO
D/U 5 12 MAX/MIN
QC 6 11 LOAD
QD 7 10 C
VSS 8
9D
B
QB
QA
CTEN
D/U
QC
QD
VSS
16-Lead Flatpack
Top View
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
VDD
A
CLK
RCO
MAX/MIN
LOAD
C
D
Two outputs have been made available to perform the cascading
function: ripple clock and maximum/minimum (MAX/MIN)
count. The MAX/MIN output produces a high-level output
pulse with a duration approximately equal to one complete cycle
of the clock while the count is zero (all outputs low) counting
down or maximum (9) counting up.
The ripple clock output (RCO) produces a low-level output pulse
under those same conditions but only while the clock input is
low. The counters easily cascade by feeding the RCO to the
enable input of the succeeding counter if parallel clocking is
used, or to the clock input if parallel enabling is used. Use the
MAX/MIN count output to accomplish look-ahead for high-
speed operation.
The devices are characterized over full military temperature
range of -55°C to +125°C.
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UT54ACTS190 pdf
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, -
50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to VIH(min) and VIL(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765
pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose 1E6 rads(Si).
8. Power does not include power contribution of any TTL output sink current.
9. Power dissipation specified per switching output.
10. This value is guaranteed based on characterization data, but not tested.
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