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PDF UT54ACTS165 Data sheet ( Hoja de datos )
| Número de pieza | UT54ACTS165 | |
| Descripción | 8-Bit Parallel Shift Registers | |
| Fabricantes | Aeroflex Circuit Technology | |
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Standard Products
UT54ACS165/UT54ACTS165
8-Bit Parallel Shift Registers
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
Complementary outputs
Direct overriding load (data) inputs
Gated clock inputs
Parallel-to-serial data conversions
1.2μ CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 16-pin DIP
- 16-lead flatpack
UT54ACS165 - SMD 5962-96558
UT54ACTS165 - SMD 5962-96559
DESCRIPTION
The UT54ACS165 and the UT54ACTS165 are 8-bit serial shift regis-
ters that, when clocked, shift the data toward serial output QH. Parallel-
in access to each stage is provided by eight individual data inputs that
are enabled by a low level at the SH/LD input. The devices feature a
clock inhibit function and a complemented serial output QH .
Clocking is accomplished by a low-to-high transition of the CLK input
while SH/LD is held high and CLK INH is held low. The functions of
the CLK and CLK INH (clock inhibit) inputs are interchangeable. Since
a low CLK input and a low-to-high transition of CLK INH will also
accomplish clocking, CLK INH should be changed to the high level
only while the CLK input is high. Parallel loading is disabled when
SH/LD is held high. Parallel inputs to the registers are enabled while
SH/LD is low independently of the levels of CLK, CLK INH or SER
inputs.
The devices are characterized over full military temperature range of
-55°C to +125°C.
FUNCTION TABLE
INPUTS
INTERNAL OUTPUTS
OUTPUTS
SH/ CLK CLK SER PARALLEL
LD INH
A . . . H QA QB QH QH
L X X X a ... h a b h h
H L L X X QA QB QH QH
H L ↑ H X H QA QG QG
H L ↑ L X L QA QG QG
H H X X X QA QB QH QH
Note:
1. Qn = The state of the referenced output one setup time prior to the Low-to-
High clock transition.PINOUTS
PINOUTS
16-Pin DIP
Top View
SH/LD 1 16 VDD
CLK 2 15 CLK INH
E 3 14 D
F 4 13 C
G 5 12 B
H 6 11 A
QH 7 10 SER
VSS 8
9 QH
SH/LD
CLK
E
F
G
H
QH
VSS
16-Lead Flatpack
Top View
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
VDD
CLK INH
D
C
B
A
SER
QH
LOGIC SYMBOL
(1)
SH/LD
(15)
CLK INH
CLK (2)
SRG8
C1 (LOAD)
≥1 C2/
SER (10)
A (11)
2D
1D
B (12)
C (13)
D (14)
E (3)
F (4)
G (5)
H (6)
1D
1D
(9)
(7) QH
QH
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
1
1 page  
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, -
50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to VIH(min) and VIL(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density ≤ 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765
pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose ≤ 1E6 rads(Si).
8. Power does not include power contribution of any TTL output sink current.
9. Power dissipation specified per switching output.
10. This value is guaranteed based on characterization data, but not tested.
5
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| PDF Descargar | [ Datasheet UT54ACTS165.PDF ] | |
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