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PDF UT54ACS164 Data sheet ( Hoja de datos )

Número de pieza UT54ACS164
Descripción 8-Bit Shift Registers
Fabricantes Aeroflex Circuit Technology 
Logotipo Aeroflex Circuit Technology Logotipo



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No Preview Available ! UT54ACS164 Hoja de datos, Descripción, Manual

Standard Products
UT54ACS164/UT54ACTS164
8-Bit Shift Registers
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
‰ AND-gated (enable/disable) serial inputs
‰ Fully buffered clock and serial inputs
‰ Direct clear
‰ 1.2μ CMOS
- Latchup immune
‰ High speed
‰ Low power consumption
‰ Single 5 volt supply
‰ Available QML Q or V processes
‰ Flexible package
- 14-pin DIP
- 14-lead flatpack
‰ UT54ACS164 - SMD 5962-96556
‰ UT54ACTS164 - SMD 5962-96557
DESCRIPTION
The UT54ACS164 and the UT54ACTS164 are 8-bit shift reg-
isters which feature AND-gated serial inputs and an asynchro-
nous clear. The gated serial inputs (A and B) permit complete
control over incoming data. A low at either input inhibits entry
of new data and resets the first flip-flop to the low level at the
next clock pulse. A high-level at both serial inputs sets the first
flip-flop to the high level at the next clock pulse. Data at the
serial inputs may be changed while the clock is high or low,
providing the minimum setup time requirements are met. Clock-
ing occurs on the low-to-high-level transition of the clock input.
The devices are characterized over full military temperature
range of -55°C to +125°C.
FUNCTION TABLE
INPUTS
OUTPUTS
CLR
L
CLK
X
A
X
B QA
QB ... QH
XLLL
H
L
X
X
QA0
QB0
QH0
H
H
H
H
QAn
QGn
H
L
X
L
QAn
QGn
H
X
L
L
QAn
QGn
PINOUTS
A
B
QA
QB
QC
QD
VSS
14-Pin DIP
Top View
A 1 14 VDD
B 2 13 QH
QA 3 12 QG
QB 4 11 QF
QC 5 10 QE
QD 6
VSS 7
9 CLR
8 CLK
14-Lead Flatpack
Top View
1 14
2 13
3 12
4 11
5 10
69
78
VDD
QH
QG
QF
QE
CLR
CLK
LOGIC SYMBOL
(9)
CLR
(8)
CLK
A (1)
(2)
B
SRG8
R
C1/
&
1D
(3)
QA
(4)
(5) QB
(6) QC
(10) QD
(11) QE
(12) QF
(13) QG
QH
Notes:
1. QA0, QB0, QH0 = the level of QA, QB or QH, respectively, before the indicated
steady-state input conditions were established.
2. QAn and QGn = the level of QA or QG before the most recent transition of
the clock; indicates a one-bit shift.
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
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UT54ACS164 pdf
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, -
50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to VIH(min) and VIL(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765
pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose 1E6 rads(Si).
8. Power does not include power contribution of any TTL output sink current
9. Power dissipation specified per switching output.
10. This value is guaranteed based on characterization data, but not tested.
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