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PDF UT54ACS139 Data sheet ( Hoja de datos )
| Número de pieza | UT54ACS139 | |
| Descripción | Dual 2-Line to 4-Line Decoders/Demultiplexers | |
| Fabricantes | Aeroflex Circuit Technology | |
| Logotipo |  |
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Standard Products
UT54ACS139/UT54ACTS139
Dual 2-Line to 4-Line Decoders/Demultiplexers
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
Incorporates two enable inputs to simplify cascading and/or
data reception
1.2μ CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 16-pin DIP
- 16-lead flatpack
UT54ACS139 - SMD 5962-96546
UT54ACTS139 - SMD 5962-96547
DESCRIPTION
The UT54ACS139 and the UT54ACTS139 are designed to be
used in high-performance memory-decoding or data-routing ap-
plications requiring very short propagation delay times.
The devices consist of two individual two-line to four-line de-
coders in a single package. The active-low enable input can be
used as a data line in demultiplexing applications.
The devices are characterized over full military temperature
range of -55°C to +125°C.
FUNCTION TABLE
ENABLE
INPUTS
G
SELECT
INPUTS
BA
OUTPUT
Y0 Y1 Y2 Y3
H XXHHHH
L L L LHHH
L LHHLHH
L HLHHLH
L HHHHHL
PINOUTS
1G
1A
1B
1Y0
1Y1
1Y2
1Y3
VSS
16-Pin DIP
Top View
IG 1 16 VDD
1A 2 15 2G
1B 3 14 2A
1Y0 4 13 2B
1Y1 5 12 2Y0
1Y2 6 11 2Y1
1Y3 7 10 2Y2
VSS 8 9 2Y3
16-Lead Flatpack
Top View
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
VDD
2G
2A
2B
2Y0
2Y1
2Y2
2Y3
LOGIC DIAGRAM
1G (1)
SELECT
1A (2)
1B (3)
2G (15)
SELECT
2A (14)
(13)
2B
(4)
1Y0
(5) 1Y1
(6) 1Y2
(7) 1Y3
(12) 2Y0
(11) 2Y1
(10) 2Y2
(9) 2Y3
1
1 page  
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, -
50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to VIH(min) and VIL(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density ≤ 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765
pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose ≤ 1E6 rads(Si).
8. Power does not include power contribution of any TTL output sink current.
9. Power dissipation specified per switching output.
10. This value is guaranteed based on characterization data, but not tested.
5
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| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet UT54ACS139.PDF ] | |
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