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PDF UT54ACTS74E Data sheet ( Hoja de datos )
| Número de pieza | UT54ACTS74E | |
| Descripción | Dual D Flip-Flops | |
| Fabricantes | Aeroflex Circuit Technology | |
| Logotipo |  |
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UT54ACTS74E
Dual D Flip-Flops with Clear & Preset
July, 2013
Datasheet
www.aeroflex.com/Logic
FEATURES
• m CRH CMOS process
- Latchup immune
• High speed
• Low power consumption
• Wide power supply operating range from 3.0V to 5.5V
• Available QML Q or V processes
• 14-lead flatpack
• UT54ACTS74E-SMD- 5962-96535
DESCRIPTION
The UT54ACTS74E contains two independent D-type positive
triggered flip-flops. A low level at the Preset or Clear inputs
sets or resets the outputs regardless of the levels of the other
inputs. When Preset and Clear are inactive (high), data at the
D input meeting the setup time requirement is transferred to the
outputs on the positive-going edge of the clock pulse. Follow-
ing the hold time interval, data at the D input may be changed
without affecting the levels at the outputs.
The device is characterized over full HiRel temperature range
of -55C to +125C.
FUNCTION TABLE
PRE
L
H
L
H
H
H
INPUTS
CLR
CLK
HX
LX
LX
H
H
HL
OUTPUT
D QQ
XHL
X LH
X H1 H1
HHL
L LH
X Qo Qo
Note:
1. The output levels in this configuration are not guaranteed to meet the mini-
mum levels for VOH if the lows at preset and clear are near VIL maximum.
In addition, this configuration is nonstable; that is, it will not persist when
either preset or clear returns to its inactive (high) level.
PINOUTS
CLR1
D1
CLK1
PRE1
Q1
Q1
VSS
14-Lead Flatpack
TopView
1 14
2 13
3 12
4 11
5 10
69
78
VDD
CLR2
D2
CLK2
PRE2
Q2
Q2
LOGIC SYMBOL
(4)
PRE1
(3)
CLK1
(2)
D1
(1)
CLR1
(10)
PRE2
(11)
CLK2
(12)
D2
(13)
CLR2
S
C1
D1
R
(5) Q1
(6) Q1
(9) Q2
(8) Q2
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC
Publication 617-12.
1
1 page  
Ptotal1 Power dissipation 2, 8
Ptotal2 Power dissipation 2, 8
IDDQ Quiescent Supply Current
IDDQ Quiescent Supply Current Delta
CIN Input capacitance 5
COUT Output capacitance 5
CL = 50pF
VDD = 4.5V to 5.5V
CL = 50pF
VDD = 3.0V to 3.6V
VIN = VDD or VSS
VDD from 3.0V to 5.5V
For input under test
VIN = VDD - 2.1V
For all other inputs
VIN = VDD or VSS
VDD = 5.5V
= 1MHz
VDD = 0V
= 1MHz
VDD = 0V
1.0 mW/
MHz
0.5 mW/
MHz
10 A
1.6 mA
15 pF
15 pF
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%,
as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed
to VIH(min) and VIL(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765pF/
MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose 1E6 rads(Si) per MIL-STD-883 Method 1019.
8. Power dissipation specified per switching output.
9. Guaranteed by characterization, but not tested.
5
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet UT54ACTS74E.PDF ] | |
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