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PDF LC87FBG08A Data sheet ( Hoja de datos )

Número de pieza LC87FBG08A
Descripción 8-bit 1-chip Microcontroller
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Ordering number : ENA2046B
LC87FBG08A
CMOS IC
8K-byte FROM and 256-byte RAM integrated
8-bit 1-chip Microcontroller
http://onsemi.com
Overview
The LC87FBG08A is an 8-bit microcontroller that, integrates on a single chip a number of hardware features such as
8K-byte flash ROM, 256-byte RAM, an On-chip-debugger, 16-bit timers/counters, a 16-bit timer/counter, two 8-bit
timers, a base timer serving as a time-of-day clock, a synchronous SIO interface, an asynchronous/synchronous SIO
interface, a UART interface, two 12-bit PWM channels, a 9-channel AD converter, a system clock frequency divider,
an internal high-accuracy oscillator, a reference voltage generator circuit, an internal reset and an interrupt feature.
Features
Flash ROM
8192 × 8 bits
Capable of On-board programming
with wide range (2.2 to 5.5V) of voltage source.
Block-erasable in 128 byte units
Writable in 2-byte units
RAM
256 × 9 bits
Package Form
SSOP24 (225mil) : Lead-/Halogen-free type
SSOP24 (275mil) : Lead-/Halogen-free type
(build-to-order)
VCT24 (3×3) : Lead-/Halogen-free type
Package Dimensions
unit : mm (typ)
3287
6.5
24 13
1
(0.5)
0.5
12
0.22
0.15
SANYO : SSOP24(225mil)
* This product is licensed from Silicon Storage Technology, Inc. (USA).
Semiconductor Components Industries, LLC, 2013
May, 2013
Ver.1.01
70412HKIM 20120618-S00002 No.A2046-1/30

1 page




LC87FBG08A pdf
LC87FBG08A
Standby Function
HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) There are four ways of resetting the HALT mode.
(1) Setting the reset pin to the low level
(2) System resetting by low-voltage detection
(3) System resetting by watchdog timer
(4) Occurrence of an interrupt
HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The CF, low-/medium-/ Frequency variable RC, and crystal oscillators automatically stop operation.
Note: The oscillation of the low-speed RC oscillator is also controlled directly by the watchdog timer and its
standby-mode-time oscillation is also controlled.
2) There are five ways of resetting the HOLD mode.
(1) Setting the reset pin to the lower level.
(2) System resetting by low-voltage detection
(3) System resetting by watchdog timer
(4) Having an interrupt source established at either INT0, INT1, INT2, INT4
* INT0 and INT1 HOLD mode reset is available only when level detection is set.
(5) Having an interrupt source established at port 0.
X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer.
1) The CF, low-/medium-/ Frequency variable RC oscillators automatically stop operation.
Note: The oscillation of the low-speed RC oscillator is also controlled directly by the watchdog timer and its
standby-mode-time oscillation is also controlled.
2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained.
3) There are six ways of resetting the X'tal HOLD mode.
(1) Setting the reset pin to the low level.
(2) System resetting by watchdog timer or low-voltage detection.
(3) System resetting by watchdog timer or low-voltage detection.
(4) Having an interrupt source established at either INT0, INT1, INT2, INT4
* INT0 and INT1 HOLD mode reset is available only when level detection is set.
(5) Having an interrupt source established at port 0.
(6) Having an interrupt source established in the base timer circuit.
Note: Available only when X’tal oscillation is selected.
Onchip Debugger (flash versions only)
Supports software debugging with the microcontroller mounted on the target board.
Software break setting
Stepwise execution of instructions
Real time RAM data monitoring function
All the RAM data map contents can be monitored and rewritten on the screen when the program is running.
(Part of the SFR data cannot be rewritten.)
Two channels of on-chip debugger pins are available to be compatible with small pin count devices.
DBGP0 (P0), DBGP1 (P1)
Data Security Function (flash versions only)
Protects the program data stored in flash memory from unauthorized read or copy.
Note: This data security function does not necessarily provide absolute data security.
No.A2046-5/30

5 Page





LC87FBG08A arduino
LC87FBG08A
Continued from preceding page.
Pin Name
I/O
Description
RES
I/O External reset input / internal reset output
CF1/XT1
I Ceramic resonator or 32.768kHz crystal oscillator input pin
Pin function
General-purpose input port
CF2/XT2
I/O Ceramic resonator or 32.768kHz crystal oscillator output pin
Pin function
General-purpose I/O port
Option
No
No
No
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor.
Data can be read into any input port even if it is in the output mode.
Port Name
P00 to P07
Option selected in
units of
1 bit
Option type
1
CMOS
Output type
Pull-up resistor
Programmable (Note 1)
2 Nch-open drain
No
P10 to P17 1 bit 1 CMOS
Programmable
2 Nch-open drain
Programmable
P20 to P21 1 bit 1 CMOS
Programmable
2 Nch-open drain
Programmable
P70 - No Nch-open drain
Programmable
CF2/XT2
-
No
Ceramic resonator/32.768kHz crystal resonator
No
output Nch-open drain
(N-channel open drain when set to general-purpose
output port)
Note 1: The control of the presence or absence of the programmable pull-up resistors for port 0 and the switching
between low-and high-impedance pull-up connection is exercised in nibble (4-bit) units (P00 to 03 or
P04 to 07).
User Option Table
Option Name
Port output type
Option to be Applied on
P00 to P07
Mask version
*1
Flash-ROM
Version
Option Selected in
Units of
1 bit
P10 to P17  
1 bit
P20 to P21  
1 bit
Program start
address
- ×
*2
Low-voltage
Detect function
detection reset
function
Detect level  
Power-on reset
Power-On reset level
function
*1: Mask option selection - No change possible after mask is completed.
*2: Program start address of the mask version is 00000h.
-
-
-
-
Option Selection
CMOS
Nch-open drain
CMOS
Nch-open drain
CMOS
Nch-open drain
00000h
01E00h
Enable:Use
Disable:Not Used
7-level
8-level
No.A2046-11/30

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