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PDF LC87F5WC8A Data sheet ( Hoja de datos )

Número de pieza LC87F5WC8A
Descripción 8-bit 1-chip Microcontroller
Fabricantes ON Semiconductor 
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Ordering number : ENA1898A
LC87F5WC8A
CMOS IC
FROM 128K byte, RAM 4096 byte on-chip
8-bit 1-chip Microcontroller
http://onsemi.com
Overview
The LC87F5WC8A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of
83.3ns, integrate on a single chip a number of hardware features such as 128K-byte flash ROM (onboard rewritable),
4096byte RAM, Onchip debugging function, sophisticated 16-bit timers/counters (may be divided into 8-bit timers), a
16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit PWMs), four 8-bit timers with a prescaler, a
base timer serving as a time-of-day clock, a high-speed clock counter, two synchronous SIO ports (with automatic
block transmission/reception capabilities), an asynchronous/synchronous SIO port, two UART ports (full duplex),
four 12-bit PWM channels, an 8-bit 15-channel AD converter, a system clock frequency divider, and a 29-source 10-
vector interrupt feature.
Features
Flash ROM
Capable of on-board-programing with wide range, 2.7 to 5.5V, of voltage source.
Block erase in 128 byte units
• 131072 × 8 bits
RAM
• 4096 × 9-bits
Minimum Bus Cycle Time
83.3ns (12MHz)
125ns (8MHz)
500ns (2MHz)
VDD=2.8 to 5.5V
VDD=2.5 to 5.5V
VDD=2.2 to 5.5V
Note: Bus cycle time indicates the speed to read ROM.
* This product is licensed from Silicon Storage Technology, Inc. (USA).
Semiconductor Components Industries, LLC, 2013
May, 2013
Ver.1.00a
83111HKIM 20101201-S00003 No.A1898-1/27

1 page




LC87F5WC8A pdf
Package Dimensions
unit : mm (typ)
3151A
80
81
23.2
20.0
51
50
LC87F5WC8A
100
1
(0.58)
0.65
31
30
0.3
0.15
SANYO : QIP100E(14X20)
No.A1898-5/27

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LC87F5WC8A arduino
LC87F5WC8A
*1: Make the following connection to minimize the noise input to the VDD1 pin and prolong the backup time.
Be sure to electrically short the VSS1, VSS2, VSS3 and VSS4 pins.
(Example 1) When backup is active in the HOLD mode, the high level of the port outputs is supplied by the
backup capacitors.
Power
Supply
Back-up
capacitor
LSI
VDD1
VDD2
VDD3
VDD4
VSS1 VSS2 VSS3 VSS4
(Example 2) The high-level output at the ports is unstable when the HOLD mode backup is in effect.
Power
Supply
Back-up
capacitor
LSI
VDD1
VDD2
VDD3
VDD4
VSS1 VSS2 VSS3 VSS4
No.A1898-11/27

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