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Número de pieza KAI-4011CM
Descripción CCD IMAGE SENSOR
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No Preview Available ! KAI-4011CM Hoja de datos, Descripción, Manual

KAI-4011 IMAGE SENSOR
2048 (H) X 2048 (V) INTERLINE CCD IMAGE SENSOR
JUNE 9, 2014
DEVICE PERFORMANCE SPECIFICATION
REVISION 1.1 PS-00106

1 page




KAI-4011CM pdf
KAI-4011 Image Sensor
TABLE OF FIGURES
Figure 1: Block Diagram ................................................................................................................................................................................ 8
Figure 2: Pixel Architecture.......................................................................................................................................................................... 9
Figure 3: Vertical to Horizontal Transfer Architecture .......................................................................................................................10
Figure 4: Horizontal Register to Floating Diffusion Architecture ....................................................................................................11
Figure 5: Horizontal Register .....................................................................................................................................................................12
Figure 6: Output Architecture ...................................................................................................................................................................13
Figure 7: ESD Protection .............................................................................................................................................................................14
Figure 8: Package Pin Designations Top View....................................................................................................................................15
Figure 9: Monochrome with Microlens Quantum Efficiency..............................................................................................................18
Figure 10: Monochrome without Microlens Quantum Efficiency.....................................................................................................18
Figure 11: Color Quantum Efficiency.......................................................................................................................................................19
Figure 12: Angular Quantum Efficiency ..................................................................................................................................................20
Figure 13: Dark Current versus Temperature........................................................................................................................................20
Figure 14: Power ...........................................................................................................................................................................................21
Figure 15: Frame Rates................................................................................................................................................................................21
Figure 16: Overclock Regions of Interest ...............................................................................................................................................23
Figure 17: Output Amplifier.......................................................................................................................................................................28
Figure 18: Clock Line Capacitances ..........................................................................................................................................................29
Figure 19: Progressive Scan Operation ...................................................................................................................................................31
Figure 20: Progressive Scan Flow Chart ..................................................................................................................................................31
Figure 21: Summed Interlaced Scan Operation.....................................................................................................................................32
Figure 22: Summed Interlaced Scan Flow Chart ...................................................................................................................................32
Figure 23: Non- Summed Interlaced Scan Operation ..........................................................................................................................33
Figure 24: Non- Summed Interlaced Scan Flow Chart .........................................................................................................................33
Figure 25: Framing Timing without Binning...........................................................................................................................................34
Figure 26: Frame Timing for Vertical Binning by 2 ...............................................................................................................................34
Figure 27: Non-Summed Interlaced Scan Even Frame Timing...........................................................................................................35
Figure 28: Non-Summed Interlaced Scan Odd Frame Timing ............................................................................................................36
Figure 29: Summed Interlaced Scan Even Frame Timing ....................................................................................................................37
Figure 30: Summed Interlaced Scan Odd Frame Timing .....................................................................................................................38
Figure 31: Frame Timing Edge Alignment ..............................................................................................................................................39
Figure 32: Line Timing Single Output ......................................................................................................................................................40
Figure 33: Line Timing Dual Output .........................................................................................................................................................40
Figure 34: Line Timing Vertical Binning by 2..........................................................................................................................................41
Figure 35: Line Timing Detail .....................................................................................................................................................................42
Figure 36: Line Timing by 2 Detail ............................................................................................................................................................42
Figure 37: Line Timing Interlaced Modes................................................................................................................................................43
Figure 38: Line Timing Edge Alignment ..................................................................................................................................................44
Figure 39: Pixel Timing ................................................................................................................................................................................45
Figure 40: Pixel Timing Detail ....................................................................................................................................................................45
Figure 41: Fast Line Dump Timing ............................................................................................................................................................46
Figure 42: Electronic Shutter Line Timing ..............................................................................................................................................47
Figure 43: Integration Time Definition....................................................................................................................................................47
Figure 44: Completed Assembly ...............................................................................................................................................................51
Figure 45: Die to Package Alignment ......................................................................................................................................................52
Figure 46: Glass Drawing.............................................................................................................................................................................53
Figure 47: Glass Transmission....................................................................................................................................................................54
www.truesenseimaging.com
Revision 1.1 PS-0016 Pg 5

5 Page





KAI-4011CM arduino
KAI-4011 Image Sensor
HORIZONTAL REGISTER TO FLOATING DIFFUSION
RD R
OG H2S H2B H1S H1B H2S H2B H1S
n+ n n+
Floating
Diffusion
n- n-
n (burried channel)
p (GND)
n-
n (SUB)
Figure 4: Horizontal Register to Floating Diffusion Architecture
The HCCD has a total of 2124 pixels. The 2112 vertical shift registers (columns) are shifted into the center 2112 pixels
of the HCCD. There are 12 pixels at both ends of the HCCD, which receive no charge from a vertical shift register. The
first 12 clock cycles of the HCCD will be empty pixels (containing no electrons). The next 28 clock cycles will contain
only electrons generated by dark current in the VCCD and photodiodes. The next 2056 clock cycles will contain photo-
electrons (image data). Finally, the last 28 clock cycles will contain only electrons generated by dark current in the
VCCD and photodiodes. Of the 28 dark columns, the first and last dark columns should not be used for determining the
zero signal level. Some light does leak into the first and last dark columns. Only use the center 26 columns of the 28
column dark reference.
When the HCCD is shifting valid image data, the timing inputs to the electronic shutter (SUB), VCCD (V1, V2), and fast
line dump (FD) should be not be pulsed. This prevents unwanted noise from being introduced. The HCCD is a type of
charge coupled device known as a pseudo-two phase CCD. This type of CCD has the ability to shift charge in two
directions. This allows the entire image to be shifted out to the video L output, or to the video R output (left/right
image reversal). The HCCD is split into two equal halves of 1068 pixels each. When operating the sensor in single
output mode the two halves of the HCCD are shifted in the same direction. When operating the sensor in dual output
mode the two halves of the HCCD are shifted in opposite directions. The direction of charge transfer in each half is
controlled by the H1BL, H2BL, H1BR, and H2BR timing inputs.
www.truesenseimaging.com
Revision 1.1 PS-0016 Pg 11

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