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PDF KAI-02050 Data sheet ( Hoja de datos )
| Número de pieza | KAI-02050 | |
| Descripción | CCD IMAGE SENSOR | |
| Fabricantes | ON Semiconductor | |
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KAI-02050
1600 (H) x 1200 (V) Interline
CCD Image Sensor
Description
The KAI−02050 Image Sensor is a 2−megapixel CCD in a 2/3″
optical format. Based on the TRUESENSE 5.5 micron Interline
Transfer CCD Platform, the sensor features broad dynamic range,
excellent imaging performance, and a flexible readout architecture
that enables use of 1, 2, or 4 outputs for full resolution readout up to 68
frames per second. A vertical overflow drain structure suppresses
image blooming and enables electronic shuttering for precise exposure
control. Other features include low dark current, negligible lag, and
low smear.
The sensor shares common PGA pin-out and electrical
configurations with other devices based on the TRUESENSE
5.5 micron Interline Transfer CCD Platform, allowing a single camera
design to support multiple members of this sensor family.
Table 1. GENERAL SPECIFICATIONS
Parameter
Architecture
Total Number of Pixels
Number of Effective Pixels
Number of Active Pixels
Pixel Size
Active Image Size
Aspect Ratio
Number of Outputs
Charge Capacity
Output Sensitivity
Quantum Efficiency
Mono (−ABA)
R, G, B (−FBA)
R, G, B (−CBA)
Read Noise (f = 40 MHz)
Dark Current
Photodiode / VCCD
Typical Value
Interline CCD, Progressive Scan
1684 (H) × 1264 (V)
1640 (H) × 1240 (V)
1600 (H) × 1200 (V)
5.5 mm (H) × 5.5 mm (V)
8.8 mm (H) × 6.6 mm (V)
11.0 mm (diagonal), 2/3″ Optical Format
4:3
1, 2, or 4
20,000 electrons
34 mV/e−
44%
29%, 37%, 39%
31%, 37%, 38%
12 e− rms
7 / 100 e−/s
Dark Current Doubling Temp
Photodiode / VCCD
Dynamic Range
Charge Transfer Efficiency
Blooming Suppression
Smear
Image Lag
Maximum Pixel Clock Speed
Maximum Frame Rates
Quad / Dual / Single Output
7°C / 9°C
64 dB
0.999999
> 300 X
−100 dB
< 10 electrons
40 MHz
68 / 34 / 18 fps
Package
68 Pin PGA
64 Pin CLCC
Cover Glass
AR Coated, 2-Sides or Clear Glass
NOTE: All Parameters are specified at T = 40°C unless otherwise noted.
© Semiconductor Components Industries, LLC, 2015
August, 2015 − Rev. 8
1
www.onsemi.com
Figure 1. KAI−02050 Interline CCD
Image Sensor
Features
• Color or Monochrome Configurations
• Progressive Scan Readout
• Flexible Readout Architecture
• High Frame Rate
• High Sensitivity
• Low Noise Architecture
• Excellent Smear Performance
• Package Pin Reserved for Device
Identification
Applications
• Industrial Imaging
• Medical Imaging
• Security
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
Publication Order Number:
KAI−02050/D
1 page  
Physical Description
PGA Pin Description and Device Orientation
KAI−02050
67 65
V3T V1T
68 66
ESD
V4T
63
VDDc
61
GND
59 57
55 53
51 49
47 45 43
Rc H2SLc H1Bc H2Sc N/C H2Sd H1Bd H2SLd Rd
41
GND
39
VDDd
37
V1T
35
V3T
64 62 60
V2T VOUTc RDc
58
OGc
56
H2Bc
54
H1Sc
52
SUB
50
H1Sd
48
H2Bd
46
OGd
44 42 40
RDd VOUTd V2T
38 36
V4T DevID
Pixel (1, 1)
4
6
8
10 12
14 16
18 20
22 24 26
28 30
32 34
V4B
V2B VOUTa RDa OGa H2Ba H1Sa SUB H1Sb H2Bb OGb RDb VOUTb V2B
V4B ESD
13
57
V3B V1B VDDa GND
9 11 13 15 17 19 21 23 25
Ra H2SLa H1Ba H2Sa N/C H2Sb H1Bb H2SLb Rb
27
GND
29
VDDb
31
V1B
33
V3B
Figure 3. PGA Package Pin Designations − Top View
Table 4. PGA PACKAGE PIN DESCRIPTION
Pin Name
Description
1 V3B Vertical CCD Clock, Phase 3, Bottom
3 V1B Vertical CCD Clock, Phase 1, Bottom
4 V4B Vertical CCD Clock, Phase 4, Bottom
5
VDDa
Output Amplifier Supply, Quadrant a
6 V2B Vertical CCD Clock, Phase 2, Bottom
7
GND
Ground
8
VOUTa
Video Output, Quadrant a
9 Ra Reset Gate, Quadrant a
10
RDa
Reset Drain, Quadrant a
11
H2SLa
Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant a
12
OGa
Output Gate, Quadrant a
13
H1Ba
Horizontal CCD Clock, Phase 1, Barrier, Quadrant a
14
H2Ba
Horizontal CCD Clock, Phase 2, Barrier, Quadrant a
15
H2Sa
Horizontal CCD Clock, Phase 2, Storage, Quadrant a
16
H1Sa
Horizontal CCD Clock, Phase 1, Storage, Quadrant a
17 N/C No Connect
18
SUB
Substrate
19
H2Sb
Horizontal CCD Clock, Phase 2, Storage, Quadrant b
20
H1Sb
Horizontal CCD Clock, Phase 1, Storage, Quadrant b
21
H1Bb
Horizontal CCD Clock, Phase 1, Barrier, Quadrant b
22
H2Bb
Horizontal CCD Clock, Phase 2, Barrier, Quadrant b
23
H2SLb
Horizontal CCD Clock, Phase 1, Storage, Last Phase, Quadrant b
24
OGb
Output Gate, Quadrant b
www.onsemi.com
5
5 Page 
TYPICAL PERFORMANCE CURVES
Quantum Efficiency
Monochrome with Microlens
KAI−02050
NOTE: The PGA and CLCC versions have different quantum efficiencies due to differences in the cover glass transmission.
See Figure 32: Cover Glass Transmission for more details.
Figure 5. Monochrome with Microlens Quantum Efficiency
Monochrome without Microlens
Figure 6. Monochrome without Microlens Quantum Efficiency
www.onsemi.com
11
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| PDF Descargar | [ Datasheet KAI-02050.PDF ] | |
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