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Número de pieza | CAT28C257 | |
Descripción | 256 kb CMOS Parallel EEPROM | |
Fabricantes | ON Semiconductor | |
Logotipo | ||
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No Preview Available ! CAT28C257
256 kb CMOS Parallel
EEPROM
Description
The CAT28C257 is a fast, low power, 5 V−only CMOS Parallel
EEPROM organized as 32K x 8−bits. It requires a simple interface for
in−system programming. On−chip address and data latches,
self−timed write cycle with auto−clear and VCC power up/down write
protection eliminate additional timing and protection hardware. DATA
Polling and Toggle status bits signal the start and end of the self−timed
write cycle. Additionally, the CAT28C257 features hardware and
software write protection.
The CAT28C257 is manufactured using ON Semiconductor’s
advanced CMOS floating gate technology. It is designed to endure
100,000 program/erase cycles and has a data retention of 100 years.
The device is available in JEDEC approved 28−pin DIP or 32−pin
PLCC packages.
Features
• Fast Read Access Times: 120/150 ns
• Low Power CMOS Dissipation:
– Active: 25 mA Max.
– Standby: 150 mA Max.
• Simple Write Operation:
– On−chip Address and Data Latches
– Self−timed Write Cycle with Auto−clear
• Fast Write Cycle Time:
− 5 ms Max.
• CMOS and TTL Compatible I/O
• Automatic Page Write Operation:
− 1 to 128 Bytes in 5 ms
− Page Load Timer
• End of Write Detection:
− Toggle Bit
− DATA Polling
• Hardware and Software Write Protection
• 100,000 Program/Erase Cycles
• 100 Year Data Retention
• Commercial, Industrial and Automotive Temperature Ranges
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PDIP−28
P, L SUFFIX
CASE 646AE
PLCC−32
N, G SUFFIX
CASE 776AK
Pin Name
A0−A14
I/O0−I/O7
CE
OE
WE
VCC
VSS
NC
PIN FUNCTION
Function
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Write Enable
5 V Supply
Ground
No Connect
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
© Semiconductor Components Industries, LLC, 2009
December, 2009 − Rev. 6
1
Publication Order Number:
CAT28C257/D
1 page CAT28C257
Table 8. A.C. CHARACTERISTICS, WRITE CYCLE (VCC = 5 V ±10%, unless otherwise specified.)
28C257−12
28C257−15
Symbol
Parameter
Min Typ Max Min Typ Max Units
tWC Write Cycle Time
5 5 ms
tAS Address Setup Time
0
0
ns
tAH Address Hold Time
50
50
ns
tCS CE Setup Time
00
ns
tCH CE Hold Time
00
ns
tCW (Note 10)
CE Pulse Time
100 100
ns
tOES
OE Setup Time
00
ns
tOEH
OE Hold Time
00
ns
tWP (Note 10)
WE Pulse Width
100 100
ns
tDS Data Setup Time
50
50
ns
tDH Data Hold Time
00
ns
tINIT (Note 11)
Write Inhibit Period After Power−up
5
10 5
10 ms
tBLC (Notes 11, 12) Byte Load Cycle Time
0.1 100 0.1 100 ms
10. A write pulse of less than 20 ns duration will not initiate a write cycle.
11. This parameter is tested initially and after a design or process change that affects the parameter.
12. A timer of duration tBLC max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin; however
a transition from HIGH to LOW within tBLC max. stops the timer.
VCC − 0.3 V
0.0 V
INPUT PULSE LEVELS
2.0 V
0.8 V
REFERENCE POINTS
Figure 2. A.C. Testing Input/Output Waveform (Note 13)
13. Input rise and fall times (10% and 90%) < 10 ns.
1.3 V
1N914
DEVICE
UNDER
TEST
3.3 K
CL = 100 pF
OUT
CL INCLUDES JIG CAPACITANCE
Figure 3. A.C. Testing Load Circuit (example)
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5
5 Page CAT28C257
PACKAGE DIMENSIONS
PLCC 32
CASE 776AK−01
ISSUE O
PIN#1 IDENTIFICATION
E1 E
E2
D1
D
TOP VIEW
b1
b
D2
SIDE VIEW
e
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-016.
A2
A3
END VIEW
SYMBOL
A2
A3
b
b1
D
D1
D2
E
E1
E2
e
MIN
0.38
2.54
0.33
0.66
12.32
11.36
9.56
14.86
13.90
12.10
NOM
MAX
1.27 BSC
2.80
0.54
0.82
12.57
11.50
11.32
15.11
14.04
13.86
http://onsemi.com
11
11 Page |
Páginas | Total 13 Páginas | |
PDF Descargar | [ Datasheet CAT28C257.PDF ] |
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