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PDF EQCO62R20.3 Data sheet ( Hoja de datos )
| Número de pieza | EQCO62R20.3 | |
| Descripción | 6.25 Gbps Asymmetric Coax Equalizer | |
| Fabricantes | Microchip | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de EQCO62R20.3 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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EQCO62R20.3/EQCO31R20.3
EQCO62R20.3 6.25 Gbps Asymmetric Coax Equalizer/
EQCO31R20.3 3.125 Gbps Asymmetric Coax Equalizer
Features
• Complies with the CoaXPress v1.1 camera
standard (1)
• Supports up to 68 meters of cable at 6.25 Gbps
using high-quality coax
• Supports up to 212 meters of cable at 1.25 Gbps
using high-quality coax
• Single-chip solutions for both the camera side and
the frame grabber side, making a bidirectional
connection over a single 75Ω coax cable
• Full-Duplex, bidirectional data channel
- Downlink speeds from 1.25 Gbps up to 6.25
Gbps; differential interfacing straightforward
with internal termination resistors
- Uplink supporting 21 Mbps, allowing
nanoseconds precise triggering events driven
by the frame grabber
• Supports power distribution over the coax up to
900 mA, powering the camera through the same
coax transporting data signals
• Low power consumption (<70 mW, 1.2V supply)
• 16-Pin, 0.65 mm pin pitch, 4 mm QFN package
• Small PCB footprint for EQCO62R20 and off-chip
components, with guaranteed RF-performance
• -40°C to +85°C industrial temperature range
• Pb-free and RoHS compliant
Applications
• High-definition/high-bandwidth links to cameras
• Machine vision for semiconductor chips and
display panel inspection systems
• Military, aerospace, medical applications
• Broadcast and surveillance camera systems
• Traffic license plate and monitoring systems
• High-Speed inspection systems for food Inspection,
bottling inspection, panel inspection, etc.
• Any application requiring a single coax cable
which carries power, video data and camera
control stream.
Introduction
The EQCO62T/R20(2) chipset is a driver/equalizer
chipset that forms a bidirectional, full-duplex
communication link over a single coax cable.
The EQCO62T/R20 chipset is designed to transport up
to 6.25 Gbps over the downlink channel and to trans-
port 21 Mbps over the uplink channel. The
EQCO62T20 is designed to transmit the downlink sig-
nal at up to 6.25 Gbps and receive the uplink signal.
The EQCO62R20 is designed to receive the downlink
signal at up to 6.25 Gbps and to transmit the uplink sig-
nal. Power can be transferred over the same cable via
external inductors.
The chipset is designed to work with several types of
75Ω coaxial cables, including legacy cables as well as
thin, flexible lightweight cables.
Note 1: CoaXPress V1.1 standard. Free down-
load from the JIIA website:
http://jiia.org/en/standardization/list/
2: The EQCO31T20 and EQCO31R20 are
lower-speed versions of the EQCO62T20
and EQCO62R20, with a maximum bit
rate of 3.125 Gbps for the high-speed
downlink and the same uplink speed.
2012-2016 Microchip Technology Inc.
DS60001302B-page 1
1 page  
EQCO62R20.3/EQCO31R20.3
1.1 Pinout and Pin Description
FIGURE 1-2:
EQCO62R20.3 PIN DIAGRAM(VIEWED FROM TOP)
VCC
16
NC
15
NC VCC
14 13
GND 1
12 GND
SDIp 2
11 SDOp
SDIn 3
EQCO62R20.3
10 SDOn
GND 4
GND TAB
9 GND
5678
LFI AmpR RiseR NC
TABLE 1-1: EQCO62R20.3 PIN DESCRIPTIONS
Pin Number
Pin Name
Signal Type
Description
(TAB)
13, 16
1, 4, 9, 12
2, 3
11, 10
5
6
7
8, 14, 15
GND
VCC
GND
SDIp, SDIn
Power
Power
Power
CML Input
SDOp/SDOn CML Output
LFI Input
AmpR
Input
RiseR
Input
NC —
Use as single-point ground.
Connect to 1.2V of power supply.
Connect to ground of power supply.
Serial input positive/negative differential serial input. Connect
SDIn to shield of cable via termination network. External 15Ω
resistors required.
Serial output positive/negative differential serial output.
Output has a swing of 2x600 mV and has 2x50Ω on-chip
termination resistors.
Uplink input signal. LVTTL signal with 1.2V input swing.
External series resistor is required for 2.5V (3.9 kΩ) or 3.3V
(6.2 kΩ) input swing.
Connected to VCC by a resistor that selects output swing of
the uplink signal. Typical value is Ramp = 1.2 kΩ for rise/fall
times of 11 ns.
Connected to VCC by a resistor that selects rise time of the
uplink signal. Typical value is Rrise = 10 kΩ for rise/fall times
of 11 ns.
Do not connect. Leave these pins floating. Used for
internal testing.
2012-2016 Microchip Technology Inc.
DS60001302B-page 5
5 Page 
EQCO62R20.3/EQCO31R20.3
and power plane underneath the input pins is
recommended. For best performance, no vias should
be used in this high-speed signal path.
A large cut-out underneath the right angle BNC
connector, the AC coupling capacitors, ferrite beads
and inductor is needed for minimal parasitics.
This proposed layout is designed to be largely
independent of the used PCB-layer stack. This will
work as well for four, six or even higher numbers of
layers. Possible extra layers should have cut-outs as
large as the full proposed footprint.
FIGURE 2-3:
PCB LAYOUT OF MULTILANE COAXPRESS 0V1 DEMO BOARD PAIR
Camera Side
CD_1 CD_2 CD_3 CD_4 EQ_5
5x6.25Gb/s + 5x21Mb/s
CD_5
EQ_4 EQ_3 EQ_2 EQ_1
Host Side
2012-2016 Microchip Technology Inc.
DS60001302B-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet EQCO62R20.3.PDF ] | |
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