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PDF AK4538 Data sheet ( Hoja de datos )
| Número de pieza | AK4538 | |
| Descripción | 16Bit CODEC | |
| Fabricantes | Asahi Kasei Microsystems | |
| Logotipo |  |
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ASAHI KASEI
[AK4538]
AK4538
16Bit ∆Σ CODEC with MIC/HP/SPK-AMP
GENERAL DESCRIPTION
The AK4538 targeted at PDA and other low-power, small size applications. It features a 16-bit stereo
CODEC with a built-in Microphone-Amplifier, Headphone-Amplifier and Speaker-Amplifier. Input circuits
include a Microphone-Amplifier and an ALC (Auto Level Control) circuit. The AK4538 is available in a
52-QFN, utilizing less board space than competitive offerings.
FEATURES
1. Resolution : 16bits
2. Recording Function
• 1ch Mono Input
• 1st MIC Amplifier : +20dB or 0dB
• 2nd Amplifier with ALC : +27.5dB ∼ -8dB, 0.5dB Step
• ADC Performance : S/(N+D) : 79dB, DR, S/N : 83dB
3. Playback Function
• Digital De-emphasis Filter (tc=50/15µs, fs=32kHz, 44.1kHz, 48kHz)
• Digital Volume (0dB ∼ -127dB, 0.5dB Step, Mute)
• Stereo Line Output
- Performance : S/(N+D) : 88dB, S/N : 92dB
• Headphone-Amp
- S/(N+D) : 70dB, S/N : 90dB
- Output Power : 15mW@16Ω (HVDD=3.3V)
• Mono Speaker-Amp with ALC
- S/(N+D) : 64dB, S/N : 90dB
- BTL Output
- Output Power : 300mW@8Ω (HVDD=3.3V)
• Mono and Stereo Beep Inputs
• AUX Input
• Mono Output
4. Power Management
5. Master Clock
(1) PLL Mode
• Frequencies : 11.2896MHz, 12MHz and 12.288MHz
• Input Level : CMOS
(2) External Clock Mode
• Frequencies : 1.792MHz ∼ 12.288MHz
6. Output Master Clock Frequencies : 32fs/64fs/128fs/256fs
7. Sampling Rate
(1) PLL Mode
• 8kHz, 11.025kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
(2) External Clock Mode
• 7kHz ∼ 48kHz
8. Control mode: 4-wire Serial / I2C Bus
9. Master/Slave mode
MS0198-E-01
-1-
2003/5
1 page  
ASAHI KASEI
[AK4538]
No. Pin Name
27 NC
28 DVDD
29 DVSS
30 XTO
XTI
31
MCKI
32 M/S
33 SPP
34 SPN
35 HVDD
36 HVSS
37 HPR
38 HPL
39 MUTET
40 MIN
41 MOUT2
42 ROUT
43 LOUT
44 MOUT-
45 MOUT+
46 AUXIN-
47 AUXIN+
48 BEEPM
49 BEEPR
50 BEEPL
51 AIN
52 NC
I/O Function
- No Connect. No internal bonding.
- Digital Power Supply Pin
- Digital Ground Pin
O X’tal Output Pin
I X’tal Input Pin
I External Master Clock Input Pin
Master / Slave Mode Pin
I
“H” : Master Mode, “L” : Slave Mode
O Speaker Amp Positive Output Pin
O Speaker Amp Negative Output Pin
- Headphone Amp Power Supply Pin
- Headphone Amp Ground Pin
O Rch Headphone Amp Output Pin
O Lch Headphone Amp Output Pin
Mute Time Constant Control Pin
O
Connected to HVSS pin with a capacitor for mute time constant.
I ALC Input Pin
O Analog Mixing Output Pin
O Line Out Right Channel
O Line Out Left Channel
O Mono Line Negative Output Pin
O Mono Line Positive Output Pin
I Mono AUX Negative Input Pin
I Mono AUX Positive Input Pin
I Mono Beep Signal Input Pin
I Rch Stereo Beep Signal Input Pin
I Lch Stereo Beep Signal Input Pin
I Analog Input Pin
- No Connect. No internal bonding.
Note: All input pins except analog input pins (INT, EXT, AIN, MIN, AUXIN+, AUXIN-, BEEPM, BEEPL, and BEEPR)
should not be left floating.
MS0198-E-01
-5-
2003/5
5 Page 
ASAHI KASEI
[AK4538]
DC CHARACTERISTICS
(Ta=−10 ∼ 70°C; AVDD, DVDD, PVDD, HVDD=2.4 ∼ 3.6V)
Parameter
Symbol
min
High-Level Input Voltage
VIH 70%DVDD
Low-Level Input Voltage
VIL -
Input Voltage at AC Coupling
(Note 25)
VAC 50%DVDD
High-Level Output Voltage
(Iout=−200µA)
VOH DVDD−0.2
Low-Level Output Voltage
(Except SDA pin: Iout=200µA)
VOL
-
( SDA pin: Iout= 3mA) VOL
-
Input Leakage Current
Iin -
typ
-
-
-
-
-
-
-
Note 25. When AC coupled capacitor is connected to MCKI pin.
SWITCHING CHARACTERISTICS
(Ta=−10 ∼ 70°C; AVDD, DVDD, PVDD, HVDD=2.4 ∼ 3.6V; CL=20pF)
Parameter
Symbol
min
Master Clock Timing
Crystal Resonator Frequency
External Clock Frequency
Pulse Width Low
Pulse Width High
AC Pulse Width (Note 26)
fCLK
tCLKL
tCLKH
tACW
11.2896
1.792
0.4/fCLK
0.4/fCLK
0.4/fCLK
MCKO Output
Frequency
Duty Cycle : except fs=32kHz
fs=32kHz at 256fs (Note 27)
fMCK
dMCK
dMCK
0.224
40
LRCK Frequency
Frequency
Duty Cycle
Slave mode
Master mode
fs
Duty
Duty
7
45
Audio Interface Timing
Slave mode
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “↑” (Note 28)
BICK “↑” to LRCK Edge
(Note 28)
LRCK to SDTO (MSB) (Except I2S mode)
BICK “↓” to SDTO
SDTI Hold Time
SDTI Setup Time
Master mode
BICK Frequency
BICK Duty
BICK “↓” to LRCK
BICK “↓” to SDTO
SDTI Hold Time
SDTI Setup Time
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
tSDH
tSDS
fBCK
dBCK
tMBLR
tBSD
tSDH
tSDS
312.5
130
130
50
50
50
50
−80
−80
50
50
typ
-
-
50
33
50
64fs
50
Max
-
30%DVDD
-
-
Units
V
V
V
V
0.2 V
0.4 V
±10 µA
max
12.288
12.288
12.288
60
48
55
Units
MHz
MHz
ns
ns
ns
MHz
%
%
kHz
%
%
ns
ns
ns
ns
ns
80 ns
80 ns
ns
ns
Hz
%
80 ns
80 ns
ns
ns
Note 26. Pulse width to ground level when MCKI is connected to a capacitor in series and a resistor is connected to ground.
(Refer to Figure 4)
Note 27. PMPLL bit = “1”.
Note 28. BICK rising edge must not occur at the same time as LRCK edge.
MS0198-E-01
- 11 -
2003/5
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AK4538.PDF ] | |
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