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Número de pieza UJA1078ATW
Descripción High-speed CAN/dual LIN core system basis chip
Fabricantes NXP Semiconductors 
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UJA1078A
High-speed CAN/dual LIN core system basis chip
Rev. 2 — 28 January 2011
Product data sheet
1. General description
The UJA1078A core System Basis Chip (SBC) replaces the basic discrete components
commonly found in Electronic Control Units (ECU) with a high-speed Controller Area
Network (CAN) and two Local Interconnect Network (LIN) interfaces.
The UJA1078A supports the networking applications used to control power and sensor
peripherals by using a high-speed CAN as the main network interface and the LIN
interfaces as local sub-busses.
The core SBC contains the following integrated devices:
High-speed CAN transceiver, inter-operable and downward compatible with CAN
transceiver TJA1042, and compatible with the ISO 11898-2 and ISO 11898-5
standards
LIN transceivers compliant with LIN 2.1, LIN 2.0 and SAE J2602, and compatible with
LIN 1.3
Advanced independent watchdog (UJA1078A/xx/WD versions)
250 mA voltage regulator for supplying a microcontroller; extendable with external
PNP transistor for increased current capability and dissipation distribution
Separate voltage regulator for supplying the on-board CAN transceiver
Serial Peripheral Interface (SPI) (full duplex)
2 local wake-up input ports
Limp home output port
In addition to the advantages gained from integrating these common ECU functions in a
single package, the core SBC offers an intelligent combination of system-specific
functions such as:
Advanced low-power concept
Safe and controlled system start-up behavior
Detailed status reporting on system and sub-system levels
The UJA1078A is designed to be used in combination with a microcontroller that
incorporates a CAN controller. The SBC ensures that the microcontroller always starts up
in a controlled manner.

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UJA1078ATW pdf
NXP Semiconductors
5. Pinning information
5.1 Pinning
UJA1078A
High-speed CAN/dual LIN core system basis chip
TXDL2 1
RXDL2 2
TXDL1 3
V1 4
RXDL1 5
RSTN 6
INTN 7
EN 8
SDI 9
SDO 10
SCK 11
SCSN 12
TXDC 13
RXDC 14
TEST1 15
WDOFF 16
Fig 2. Pin configuration
UJA1078A
32 BAT
31 VEXCTRL
30 TEST2
29 VEXCC
28 WBIAS
27 LIN2
26 DLIN
25 LIN1
24 SPLIT
23 GND
22 CANL
21 CANH
20 V2
19 WAKE2
18 WAKE1
17 LIMP
015aaa185
5.2 Pin description
Table 2.
Symbol
TXDL2
RXDL2
TXDL1
V1
RXDL1
RSTN
INTN
EN
SDI
SDO
SCK
SCSN
TXDC
RXDC
TEST1
WDOFF
LIMP
Pin description
Pin Description
1 LIN2 transmit data input
2 LIN2 receive data output
3 LIN1 transmit data input
4 voltage regulator output for the microcontroller (5 V or 3.3 V depending on
SBC version)
5 LIN1 receive data output
6 reset input/output to and from the microcontroller
7 interrupt output to the microcontroller
8 enable output
9 SPI data input
10 SPI data output
11 SPI clock input
12 SPI chip select input
13 CAN transmit data input
14 CAN receive data output
15 test pin; pin should be connected to ground
16 WDOFF pin for deactivating the watchdog
17 limp home output
UJA1078A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 28 January 2011
© NXP B.V. 2011. All rights reserved.
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UJA1078ATW arduino
NXP Semiconductors
UJA1078A
High-speed CAN/dual LIN core system basis chip
SCSN
SCK
SDI
01
sampled
X MSB
02
14
03
13
04
12
15 16
01 LSB
X
SDO
X MSB
14
13
12
floating
Fig 4. SPI timing protocol
01 LSB
floating
015aaa205
6.2.2 Register map
The first three bits (A2, A1 and A0) of the message header define the register address.
The fourth bit (RO) defines the selected register as read/write or read only.
Table 3. Register map
Address bits 15, 14 and 13
000
001
010
011
Write access bit 12 = 0
0 = read/write, 1 = read only
0 = read/write, 1 = read only
0 = read/write, 1 = read only
0 = read/write, 1 = read only
Read/Write access bits 11... 0
WD_and_Status register
Mode_Control register
Int_Control register
Int_Status register
UJA1078A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 28 January 2011
© NXP B.V. 2011. All rights reserved.
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