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PDF RT5370N Data sheet ( Hoja de datos )

Número de pieza RT5370N
Descripción highly integrated MAC/BBP and 2.4 GHz RF/PA/LNA single chip
Fabricantes Ralink 
Logotipo Ralink Logotipo



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IIIIIII
Application
IEEE802.11 b/g/n Wireless Local Area Networks
USB 2.0 Wi-Fi Dongle.
RT5370
Datasheet
Revision August 30, 2010
Product Description
The RT5370 is a highly integrated MAC/BBP and 2.4
GHz RF/PA/LNA single chip with 150Mbps PHY rate
supporting. It fully complies with IEEE 802.11n and IEEE
802.11 b/g feature rich wireless connectivity at high
standards, delivers reliable, cost-effective, throughput
from an extended distance. Optimized RF architecture
and baseband algorithms provide superb performance
and low power consumption. Intelligent MAC design
deploys a high efficient DMA engine and hardware data
processing accelerators without overloading the host
processor. The RT5370 is designed to support standard
based features in the areas of security, quality of
service and international regulation, giving end users
the greatest performance anytime in any circumstance.
Features
CMOS Technology with PA, LNA, RF, Baseband,
and MAC Integrated.
1T1R Mode with 150Mbps PHY Rate for Both
Transmit and Receiving.
Legacy and High Throughput Modes
20MHz/40MHz Bandwidth
Reverse Direction Grant Data Flow and Frame
Aggregation
WEP 64/128, WPA, WPA2,TKIP, AES, WAPI
QoS-WMM, WMM-PS
WPS,PIN,PBC
Multiple BSSID Support
Functional Block Diagram
USB 2.0
Cisco CCX Support
Bluetooth Co-existence
Low Power with Advanced Power Management
Operating Systems - Windows XP 32/64, 2000,
Windows 7,Vista 32/64 , Linux, Macintosh
Order Information
Part Number Temp Range
RT5370N
-10~70
Package
Green/RoHS
Compliant 52LD QFN
(7.5mmx5.7mm)
Ralink Technology, Corp. (Taiwan)
5th F. No. 36, Taiyuan St, Jhubei City, Hsin-Chu,
Taiwan, R.O.C.
Tel: 886-3-567-8868 Fax: 886-3-567-8818
Ralink Technology, Corp. (USA)
20833 Stevens Creek Blvd, Suite 200
Cupertino CA 95014
Tel: (408) 725-8070 Fax: (408)725-8069
http://www.ralinktech.com
RF_2G_INP/
RF_2G_INN
RF_PA_OUTP/
RF_PA_OUTN
LNA
PA
RF
receiver
RF
transmitter
Baseband
MAC/
Packet
Buffer/
Encrption
Engine
USB
System
Control
USB bus
EEPROM/GPIO
/LED
digital controlled
RF
DSRT5370_V1.0_083010
Form No.QS-073-F02
Rev.1
-I-
Kept byDCC
Ret. Time5 Years

1 page




RT5370N pdf
17 VDDA
18 VRES
PLL Power: 2 pins
36,37 V12A
Core Power: 2 pins
9,35 VDD
IO Power:1 pins
26 VCCIO
Misc.: 2 pins
11 RST_N
25 TEST_EN
GND: exposed pad
1.3 Strapping Pin
Pin Name
28 LED_RDYG_N
21 GPIO8
22 GPIO9
*Notation of Type:
I : input
O : output
IO : bi-direction
OD : open-drain
P : power
RT5370
Datasheet
Revision August 30, 2010
P 3.3 V USB power
Connect to external 8.2K resistor (the 8.2K resistor
IO connects one end to VRES and another end to PCB
ground)
P 1.2V PLL power
P 1.2V core power
P 3.3V IO power
I
0: reset the whole chip
1: normal function active
I 1: enable test mode. For normal function, tie to GND.
Type*
IO
IO
IO
Description
0: normal mode
1: RF_BIST mode
0: use internal electrical fuse
1: use external EEPROM
0: use internal program memory
1: use external program memory
DSRT5370_ V1. 0_083010
Form No.QS-073-F02
Rev.1
Kept byDCC
-3-
Ret. Time5 Years

5 Page





RT5370N arduino
RT5370
Datasheet
0 W1C RST_DTX_IDX0 Write 1 to reset to TX_DMATX_IDX0 to 0
Revision August 30, 2010
1’b0
DELAY_INT_CFG (offset:0x0210,default :0x00000000)
Bits Type Name
Description
31 RW TXDLY_INT_EN 1: Enable TX delayed interrupt mechanism.
0: Disable TX delayed interrupt mechanism.
30:24 RW TXMAX_PINT
Specified Max # of pended interrupts.
When the # of pended interrupts equal or grater than the value
specified here or interrupt pending time reach the limit (See bellow),
an Final TX_DLY_INT is generated.
Init Value
1’b0
7’b0
23:16 RW TXMAX_PTIME
Set to 0 will disable pending interrupt count check
Specified Max pending time for the internal TX_DONE_INT0-5. When
the pending time equal or grater TXMAX_PTIME x 20us or the # of
pended TX_DONE_INT0-5 equal or grater than TXMAX_PINT (see
above), an Final TX_DLY_INT is generated
8’b0
15 RW RXDLY_INT_EN
14:8 RW RXMAX_PINT
Set to 0 will disable pending interrupt time check
1: Enable RX delayed interrupt mechanism.
0: Disable RX delayed interrupt mechanism.
Specified Max # of pended interrupts.
When the # of pended interrupts equal or grater than the value
specified here or interrupt pending time reach the limit (See bellow),
an Final RX_DLY_INT is generated.
1’b0
7’b0
Set to 0 will disable pending interrupt count check
7:0 RW RXMAX_PTIME Specified Max pending time for the internal RX_DONE_INT. When the 8’b0
pending time equal or grater RXMAX_PTIME x 20us or , the # of
pended RX_DONE_INT equal or grater than RXMAX_PCNT (see
above), an Final RX_DLY_INT is generated
Set to 0 will disable pending interrupt time check
WMM_AIFSN_CFG (offset:0x0214,default :0x00000000)
Bits Type Name
Description
31:16
Reserved
15:12 RW AIFSN3
WMM parameter AIFSN3
11:8 RW AIFSN2
WMM parameter AIFSN2
7:4 RW AIFSN1
WMM parameter AIFSN1
3:0 RW AIFSN0
WMM parameter AIFSN0
Init Value
4’h0
4’h0
4’h0
4’h0
WMM_CWMIN_CFG (offset:0x0218,default :0x00000000)
Bits Type Name
Description
31:16
Reserved
15:12 RW CW_MIN3
WMM parameter Cw_min3
11:8 RW CW_MIN2
WMM parameter Cw_min2
7:4 RW CW_MIN1
WMM parameter Cw_min1
3:0 RW CW_MIN0
WMM parameter Cw_min0
Init Value
4’h0
4’h0
4’h0
4’h0
WMM_CWMAX_CFG (offset:0x021C,default :0x00000000)
Bits Type Name
Description
31:16
Reserved
15:12 RW CW_MAX3
WMM parameter Cw_max3
11:8 RW CW_MAX2
WMM parameter Cw_max2
7:4 RW CW_MAX1
WMM parameter Cw_max1
3:0 RW CW_MAX0
WMM parameter Cw_max0
DSRT5370_ V1. 0_083010
Form No.QS-073-F02
Rev.1
Kept byDCC
Init Value
4’h0
4’h0
4’h0
4’h0
-9-
Ret. Time5 Years

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