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PDF 24AA044 Data sheet ( Hoja de datos )
| Número de pieza | 24AA044 | |
| Descripción | EEPROM | |
| Fabricantes | Microchip | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de 24AA044 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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24AA044
4K I2C™ Serial EEPROM
Device Selection Table
Part
Number
VCC Range
Max Clock
Frequency
24AA044 1.7V-5.5V
1 MHz(1)
Note 1: 400 kHz for 1.8V ≤ VCC < 2.2V
100 kHz for VCC < 1.8V
Temp.
Range
I, E
Features:
• Single Supply with Operation from 1.7V to 5.5V
• Low-Power CMOS Technology:
- Read current 400 A, max
- Standby current 1 A, max at 85°C
• 2-Wire Serial Interface, I2C™ Compatible
• Cascadable up to Four Devices
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 1 MHz, 400 kHz, and 100 kHz Clock Compatibility
• Page Write Time 5 ms Maximum
• Self-timed Erase/Write Cycle
• 16-Byte Page Write Buffer
• Hardware Write-Protect
• ESD Protection >4,000V
• More than 1 Million Erase/Write Cycles
• Data Retention >200 Years
• Factory Programming Available
• Packages include 8-lead PDIP, SOIC, TSSOP,
UDFN and MSOP
• RoHS Compliant
• Temperature Ranges:
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C
Description:
The Microchip Technology Inc. 24AA044 is a 4 Kbit
Serial Electrically Erasable PROM with a voltage
range of 1.7V to 5.5V. The device is organized as two
blocks of 256 x 8-bit memory with a 2-wire serial
interface. Low-current design permits operation with
standby and active currents of only 1 A and 400 A,
respectively. The device has a page write capability for
up to 16 bytes of data. Functional address lines allow
the connection of up to four 24AA044 devices on the
same bus for up to 16K bits of contiguous EEPROM
memory. The device is available in the standard 8-pin
PDIP, 8-pin SOIC (3.90 mm), TSSOP, 2x3 UDFN and
MSOP packages.
Package Types
PDIP/SOIC/TSSOP/MSOP
UDFN
NC 1
A1 2
A2 3
VSS 4
8 VCC
NC 1
7 WP
A1 2
A2 3
6 SCL VSS 4
5 SDA
8 VCC
7 WP
6 SCL
5 SDA
Block Diagram
A1 A2
WP
HV Generator
I/O
Control
Logic
Memory
Control
Logic
XDEC
EEPROM
Array
SDA SCL
VCC
VSS
Write-Protect
Circuitry
YDEC
Sense Amp.
R/W Control
2014 Microchip Technology Inc.
DS20005286A-page 1
1 page  
24AA044
2.0 PIN DESCRIPTIONS
Pin Function Table
Name
PDIP
NC
A1
A2
VSS
SDA
SCL
WP
VCC
1
2
3
4
5
6
7
8
SOIC
1
2
3
4
5
6
7
8
TSSOP
1
2
3
4
5
6
7
8
UDFN
1
2
3
4
5
6
7
8
MSOP
1
2
3
4
5
6
7
8
Description
Not Connected
Chip Address Input
Chip Address Input
Ground
Serial Address/Data I/O
Serial Clock
Write-Protect Input
+1.7 to 5.5V Power Supply
2.1 Serial Data (SDA)
SDA is a bidirectional pin used to transfer addresses
and data into and out of the device. It is an open-drain
terminal; therefore, the SDA bus requires a pull-up
resistor to VCC (typical 10 k for 100 kHz, 2 k for
400 kHz and 1 MHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2.2 Serial Clock (SCL)
The SCL input is used to synchronize the data transfer
from and to the device.
2.3 Chip Address Inputs (A1, A2)
The levels on the A1 and A2 inputs are compared with
the corresponding bits in the slave address. The chip is
selected if the compare is true.
Up to four 24AA044 devices may be connected to the
same bus by using different Chip Select bit combina-
tions. These inputs must be connected to either VCC or
VSS.
2.4 Write-Protect (WP)
WP is the hardware write-protect pin. It must be tied to
VCC or VSS. If tied to Vcc, hardware write protection is
enabled. If WP is tied to Vss, the hardware write
protection is disabled.
2.5 Noise Protection
The 24AA044 employs a VCC threshold detector circuit
which disables the internal erase/write logic if the VCC
is below 1.35V at nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation, even on a noisy bus.
3.0 FUNCTIONAL DESCRIPTION
The 24AA044 supports a bidirectional, 2-wire bus
and data transmission protocol. A device that sends
data onto the bus is defined as transmitter, while a
device receiving data is defined as receiver. The bus
has to be controlled by a master device that gener-
ates the Serial Clock (SCL), controls the bus access
and generates the Start and Stop conditions, while
the 24AA044 works as slave. Both master and slave
can operate as transmitter or receiver, but the master
device determines which mode is activated.
2014 Microchip Technology Inc.
DS20005286A-page 5
5 Page 
24AA044
FIGURE 8-2:
RANDOM READ
BUS ACTIVITY
MASTER
SDA LINE
S
T
A
R
T
S
Control
Byte
BUS ACTIVITY
Array
Address (n)
A
C
K
S
T
A
R
T
S
A
C
K
Control
Byte
Data (n)
A
C
K
S
T
O
P
P
N
O
A
C
K
FIGURE 8-3:
SEQUENTIAL READ
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
Control
Byte
Data (n)
Data (n + 1)
Data (n + 2)
AA
CC
KK
AA
CC
KK
Data (n + x)
S
T
O
P
P
N
O
A
C
K
2014 Microchip Technology Inc.
DS20005286A-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 24AA044.PDF ] | |
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