DataSheet.es    


PDF K4D261638K-LC50 Data sheet ( Hoja de datos )

Número de pieza K4D261638K-LC50
Descripción 128Mbit GDDR SDRAM
Fabricantes Samsung 
Logotipo Samsung Logotipo



Hay una vista previa y un enlace de descarga de K4D261638K-LC50 (archivo pdf) en la parte inferior de esta página.


Total 18 Páginas

No Preview Available ! K4D261638K-LC50 Hoja de datos, Descripción, Manual

K4D261638K
128M GDDR SDRAM
128Mbit GDDR SDRAM
2M x 16Bit x 4 Banks
Graphic Double Data Rate
Synchronous DRAM
Revision 1.3
July 2007
Notice
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
- 1 /19 -
Rev. 1.3 July 2007

1 page




K4D261638K-LC50 pdf
K4D261638K
128M GDDR SDRAM
5.0 INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol
Type
Function
CK, CK*1
Input
The differential system clock Input.
All of the inputs are sampled on the rising edge of the clock except DQ’s and DM’s that are
sampled on both edges of the DQS.
CKE
Input
Activates the CK signal when high and deactivates the CK signal when low. By deactivating
the clock, CKE low indicates the Power down mode or Self refresh mode.
CS enables the command decoder when low and disabled the command decoder when high.
CS
Input
When the command decoder is disabled, new commands are ignored but previous operations
continue.
RAS
Input
Latches row addresses on the positive going edge of the CK with RAS low. Enables row
access & precharge.
CAS
Input
Latches column addresses on the positive going edge of the CK with CAS low. Enables col-
umn access.
WE
Input
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
LDQS,UDQS
Input/Output
Data input and output are synchronized with both edge of DQS.
For the x16, LDQS corresponds to the data on DQ0-DQ7 ; UDQS corresponds to the data on
DQ8-DQ15.
LDM,UDM
Input
Data in Mask. Data In is masked by DM Latency=0 when DM is
high in burst write. For the x16, LDM corresponds to the data on DQ0-DQ7 ; UDM correspons
to the data on DQ8-DQ15.
DQ0 ~ DQ15
Input/Output
Data inputs/Outputs are multiplexed on the same pins.
BA0, BA1
Input
Selects which bank is to be active.
A0 ~ A11
Input
Row/Column addresses are multiplexed on the same pins.
Row addresses : RA0 ~ RA11, Column addresses : CA0 ~ CA8.
VDD/VSS
Power Supply
Power and ground for the input buffers and core logic.
VDDQ/VSSQ
Power Supply
Isolated power supply and ground for the output buffers to provide improved noise immunity.
VREF
Power Supply
Reference voltage for inputs, used for SSTL interface.
NC/RFU
No connection/
Reserved for future use
This pin is recommended to be left "No connection" on the device
*1 : The timing reference point for the differential clocking is the cross point of CK and CK.
For any applications using the single ended clocking, apply VREF to CK pin.
- 5 /19 -
Rev. 1.3 July 2007

5 Page





K4D261638K-LC50 arduino
K4D261638K
128M GDDR SDRAM
9.0 AC & DC OPERATING CONDITIONS
9.1 POWER & DC OPERATING CONDITIONS(SSTL_2 In/Out)
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 65°C)
Parameter
Symbol
Min
Typ
Max Unit
Note
Device Supply voltage
Output Supply voltage
Reference voltage
Termination voltage
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
Output leakage current
VDD
VDDQ
VREF
Vtt
VIH
VIL
VOH
VOL
IIL
IOL
2.375
2.375
0.49*VDDQ
VREF-0.04
VREF+0.15
-0.30
Vtt+0.76
-
-5
-5
2.50
2.50
-
VREF
-
-
-
-
-
-
2.625
2.625
0.51*VDDQ
VREF+0.04
VDDQ+0.30
VREF-0.15
-
Vtt-0.76
5
5
V
V
V
V
V
V
V
V
uA
uA
1, 7
1, 7
2
3
4
5
IOH=-15.2mA
IOL=+15.2mA
6
6
Note :
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VREF is expected to equal 0.50*VDDQ of the transmitting device and to track variations in the DC level of the same. Peak to peak noise on the VREF
may not exceed + 2% of the DC value. Thus, from 0.50*VDDQ, VREF is allowed + 25mV for DC error and an additional + 25mV for AC noise.
3. Vtt of the transmitting device must track VREF of the receiving device.
4. VIH(max.)= VDDQ +1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate.
5. VIL(mim.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate.
6. For any pin under test input of 0V < VIN < VDD is acceptable. For all other pins that are not under test VIN=0V.
7. For K4D261638K-LC50, VDD & VDDQ = 2.375V to 2.7V.
9.2 DC CHARACTERISTICS
Recommended operating conditions Unless Otherwise Noted ( TA=0 to 65°C)
Parameter
Symbol
Test Condition
Operating Current
(One Bank Active)
Precharge Standby Current
in Power-down mode
Precharge Standby Current
in Non Power-down mode
Active Standby Current
power-down mode
Active Standby Current in
in Non Power-down mode
Operating Current
( Burst Mode)
Refresh Current
Self Refresh Current
Note :
1. Measured with output open.
2. Current meassured at VDD(max).
3. Refresh period is 32ms.
ICC1
ICC2P
ICC2N
ICC3P
ICC3N
ICC4
ICC5
ICC6
Burst Lenth=2 tRC tRC(min)
IOL=0mA, tCC= tCC(min)
CKE VIL(max), tCC= tCC(min)
CKE VIH(min), CS VIH(min),
tCC= tCC(min).
CKE VIL(max), tCC= tCC(min)
CKE VIH(min), CS VIH(min),
tCC= tCC(min) .
IOL=0mA ,tCC= tCC(min), Page Burst,
All Banks activated.
tRC tRFC(min)
CKE 0.2V
Version
-40 -50
200 180
45 40
70 60
85 70
135 110
350 300
200 180
10 10
Unit Note
mA 1, 2
mA 1, 2
mA 1, 2
mA 1, 2
mA 1, 2
mA 1, 2
mA 1, 2,3
mA 1, 2
- 11 /19 -
Rev. 1.3 July 2007

11 Page







PáginasTotal 18 Páginas
PDF Descargar[ Datasheet K4D261638K-LC50.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
K4D261638K-LC50128Mbit GDDR SDRAMSamsung
Samsung

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar