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PDF CH7001C Data sheet ( Hoja de datos )

Número de pieza CH7001C
Descripción VGA to NTSC/PAL Encoder
Fabricantes ETC 
Logotipo ETC Logotipo



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CHRONTEL
CH7001C
VGA to NTSC/PAL Encoder
Features
• Enhanced bandwidth and signal-to-noise ratio for
higher video performance
• Integrated triple video rate 8-bit analog to digital
converters for input RGB
• 3-line digital vertical filtering with pin-
programmable characteristics for optimum anti-
flicker and resolution
• On-chip phase-locked loop generates sampling
clock from VGA horizontal sync
• Enhanced power management for selective circuit
power-down
• Simultaneous composite/S-video output
• Horizontal and vertical position control
• Pin-programmable underscan/overscan mode
• On-chip reference generation and loop filter
• CMOS technology in 44-pin PLCC
• 5V supply
Description
Chrontel’s CH7001C VGA to NTSC/PAL encoder is a
stand-alone integrated circuit that converts analog VGA
inputs directly into 525-line (M) NTSC or 625-line
(B, D, G, H, I) PAL composite video and S-video
outputs.
This circuit integrates a digital NTSC/PAL encoder
with 8-bit ADC and DAC interfaces, a 3-line vertical
filter and low-jitter phase-locked loop to create
outstanding quality video with 24-bits-per-pixel proces-
sing throughout the entire signal path.
A high level of integration and performance makes the
CH7001C ideal for a variety of stand-alone and system-
level integration solutions, including notebook
computers and PC add-on graphics cards.
HORIZONTAL, VERTICAL
POSITION CONTROL
STROBE CLKOUT CLKEN* NTSC/PAL* PD[1:0] VDD DVDD AVDD RSET VREF1 VREF2
UNDERSCAN
MS[1:0]
R
G
B
H
V
BLANKING
H,V SYNC
GENERATOR
ADC
ADC
ADC
VERTICAL
FILTER
SCAN-RATE
CONVERTER
COLOR
SPACE
CONVERTER
PLL
SYSTEM CLOCKS
Y
FILTER
U
FILTER
RSET
VREF
M
U DAC
X
Σ DAC
M
UX
X
Σ
DAC
V
FILTER
M
U
X
X
BLANKING COLOR-BURST
CONTROL
SIN + COSINE
GENERATOR
OSC
Figure 1: Functional Block Diagram
Y
CVBS
C
201-0000-028 Rev 3.0, 6/2/99
1

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CH7001C pdf
CHRONTEL
CH7001C
Table 1 Pin Description (continued)
Pin
Type
Symbol
33 In UNDERSCAN
34 In
V
35 In
H
36 — TEST*
39 In VREF2
41 In VREF1
Description
Underscan Enable Pin (active high, internal pull-up)
A logical HIGH input to UNDERSCAN results to an output screen
that has approximately 12.5% horizontal underscan. This pin may
be connected directly to the power supply or ground.
Vertical Sync Input
This pin accepts the vertical sync output from the VGA card. The
capacitive loading on this pin should kept to a minimum.
Horizontal Sync Input
This pin accepts the horizontal sync output from the VGA card. The
capacitive loading on this pin should kept to a minimum. Please
refer to Application Note 11 “PC Board Layout Considerations
for CH7001C.
Test Pin (active low, internal pull-up)
Connect a capacitor in the range of 2.2uF - 4.7uF from this pin
to GND to ensure proper functionality of the UNDERSCAN/
OVERSCAN feature.
Internal Voltage Reference
VREF2 provides a typical 2.5V reference that is used as an internal
bias to the ADCs. A 0.1 µF decoupling capacitor should be
connected between VREF2 and ground.
ADC Voltage Reference Input / Output
VREF1 provides a typical 1.235V reference that sets the RGB input
full scale at 0.75V. A 0.1 µF decoupling capacitor should be
connected between VREF1 and ground. VREF1 may also be forced
by external reference.
Optional Output Filter
Y,C, CVBS
75 Ohms
47pF
1.2uH
150pF
1.2uH
1
270pF
OUTPUT
Figure 3: Optional Output Filter
201-0000-028 Rev 3.0, 6/2/99
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CH7001C arduino
CHRONTEL
CH7001C
Programmability
All operational modes of the CH7001C are accessed directly through the package pins, making the CH7001C
programmable without the use of an additional microcontroller. Some of the programmable features are: horizontal
overscan/underscan control, NTSC or PAL operation, selectable anti-flicker filter modes, and adjustable horizontal
and vertical display positioning capabilities.
Horizontal Overscan/Underscan
Horizontal underscan mode is enabled via the UNDERSCAN pin. By setting this pin high, the resulting output
screen experiences a 12.5% horizontal underscan.
The CH7001C also implements an overscan/underscan mode that is controllable through the PC. Software control
is available only when the underscan input is inactive (i.e., UNDERSCAN = 0) and is accomplished by
programming the length (in VGA line periods) of the vertical sync pulse.
When the CH7001C detects the vertical sync pulse as having fewer than eight VGA line periods, the device operates
in overscan mode; when it detects the vertical sync pulse as having more than eight VGA line periods, it operates in
underscan mode. The CH7001C determines the number of VGA line periods through an internal circuitry that
continuously analyzes the width of the VGA vertical sync input.
Software control is overridden if the underscan input is set high.
NTSC or PAL Operation
Composite and S-video outputs are supported in either NTSC or PAL format, as shown in Figures 8 through 10.
These outputs can be conveniently switched to either format via the NTSC/PAL* pin. If the NTSC/PAL* pin is set
low, PAL output format is selected. If the NTSC/PAL* is set high, NTSC output format is selected. See Figures 11
through 16 on pages 14 through 16 for illustrations of the composite and S-video output waveforms.
A B C D EF
G
H
Figure 8: NTSC / PAL Composite Output
201-0000-028 Rev 3.0, 6/2/99
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