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PDF CGS3317M Data sheet ( Hoja de datos )

Número de pieza CGS3317M
Descripción CMOS Crystal Clock Generators
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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No Preview Available ! CGS3317M Hoja de datos, Descripción, Manual

September 1995
Revised March 1999
CGS3311 • CGS3312 • CGS3313 • CGS3314 • CGS3315 •
CGS3316 • CGS3317 • CGS3318 • CGS3319
CMOS Crystal Clock Generators
General Description
The CGS3311, CGS3312, CGS3313, CGS3314,
CGS3315, CGS3316, CGS3317, CGS3318 and CGS3319
devices are designed for Clock Generation and Support
(CGS) applications up to 110 MHz. The CGS331x series of
devices are crystal controlled CMOS oscillators requiring a
minimum of external components. The 331x devices pro-
vide selectable output divide ratio (and selectable crystal
drive level). The circuit is designed to operate over a wide
frequency range using fundamental model or overtone
crystals.
Features
s Fairchild’s CGS family of devices for high frequency
clock source applications
s Crystal frequency operation range:
fundamental: 10 MHz to 100 MHz typical
3rd or 5th overtone: 10 MHz to 85 MHz
s Programmable oscillator drive
s Selectable fast output edge rates
s Output symmetry circuit to adjust 50% duty cycle point
between CMOS and TTL levels
s Output current drive of 48 mA for IOL/IOH
s FACTCMOS output levels
s Output has high speed short circuit protection
s Basic oscillator type: Pierce
s Hysteresis inputs to improve noise margin
Ordering Code:
Order Number Package Number Package Description
CGS3311M
M08A
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
CGS3312M
M08A
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
CGS3313M
M08A
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
CGS3314M
M08A
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
CGS3315M
M08A
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
CGS3316M
M08A
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
CGS3317M
M08A
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
CGS3318M
M08A
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
CGS3319M
M08A
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
FACTis a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS010980.prf
www.fairchildsemi.com

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CGS3317M pdf
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC)
DC Input Voltage Diode Current (IIK)
DC Input Voltage (VI)
DC Output Diode Current (IOK)
DC Output Voltage (VO)
DC Output Source
or Sink Current (IO)
Storage Temperature (TSTG)
Junction Temperature (TJ)
SOIC
0.5V to 7.0V
±9 mA
0.5V to 7.0V
±20 mA
-0.5V to VCC + 0.5V
±70 mA
55°C to 150°C
140°C/W
Recommended Operating
Conditions
Supply Voltage (VCC)
4.5V to 5.5V
Input Voltage (VI)
0V to 5.5V
Output Voltage (VO)
0V to VCC V
Operating Temperature (TA)
40° to +85°C
Note 1: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the DC and AC
Electrical Characteristics tables are not guaranteed at the absolute maxi-
mum ratings. The Recommended Operating Conditions will define the con-
ditions for actual device operation.
DC Electrical Characteristics
Symbol
VIHTTL
VILTTL
VIHCMOS
VILCMOS
VIN3L_H
VIN3L_1/2
VIN3L_L
VOH
VOL
IIHRES
IILRES
IIHENAB
IILENAB
IIHOSC
IILOSC
IOZH
Parameter
Minimum HIGH Level
Input Voltage,
TTL Level Inputs (OEH, OEL)
Maximum LOW Level
Input Voltage, TTL Level
Inputs (OEH, OEL)
Minimum HIGH Level
Input Voltage. CMOS
Level Inputs (DIVA)
Maximum LOW Level
Input voltage. CMOS
Level Inputs (DIVA)
Minimum Logic 1 Input
for Three Level Input
(DIVB, OSC_DR)
Minimum Logic 1/2 Input
for Three Level Input
(DIVB, OSC_DR)
Maximum Logic 0 Input
Level Three Level Input
(DIVB, OSC_DR)
Minimum HIGH Level
Output Voltage
Minimum LOW Level
Output Voltage
Input Current for Pins
DIVB, OSC_DR, and
DIVA (Input is Logic HIGH)
Input Current for Pins
DIVB, OSC_DR, and
DIVA (Input is Logic LOW)
Input Current for
Enable Pin OEL
Input Current for
Enable Pin OEH
Input Current for OSC_IN Pin
(Indicates Bias Resistance)
Input Current for OSC_IN Pin
(Indicates Bias Resistance)
Output Disabled Current
(Output HIGH)
TA = +25°C
VCC Guaranteed Limits
(V) Typ Min Max
4.5 2.0
5.5 2.0
4.5 0.8
5.5 0.8
4.5 3.15
5.5 3.85
4.5 1.35
5.5 1.65
4.5 4.05
5.5 4.95
4.5 1.8 2.7
5.5 2.2 3.3
4.5 0.45
5.5 0.45
4.5 4.49
5.5 5.49
4.5
5.5
4.5 0.001
5.5 0.001
4.5
5.5
5.5
4.40
5.40
3.86
4.86
220
0.1
0.1
0.44
0.44
360
5.5
220
360
5.5 90 160
5.5 90 160
5.5 20 100
5.5 20 100
4.5 3.0
5.5 3.0
TA = −40° C to +85°C
Min
2.0
2.0
3.15
3.85
1.35
1.65
4.05
4.95
1.8
2.2
4.40
5.40
3.76
4.76
200
Max
0.8
0.8
2.7
3.3
0.45
0.45
0.1
0.1
0.44
0.44
380
Units Conditions
V
V
V
V
V
V
V
V IOUT = −50µA
IOH = −48 mA
VIN = VIH or VIH
V IOUT = 50µA
IOL = +48mA
VIN = VIL or VIH
µA VIN = 5.5V
200
380
µA VIN = 0.0V
85 175 µA VIN = 5.5V
85
175
µA VIN = 0.0V
20 125 µA VIN = 5.5V
20
125
µA VIN = 0.0V
5.0 µA VOUT = VCC
5.0
5 www.fairchildsemi.com

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