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PDF CGS2536V Data sheet ( Hoja de datos )
| Número de pieza | CGS2536V | |
| Descripción | Commercial/ Industrial Quad 1 to 4 Clock Drivers | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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September 1995
CGS2536V
Commercial Quad 1 to 4 Clock Drivers
CGS2536TV
Industrial Quad 1 to 4 Clock Drivers
General Description
These Clock Generation and Support clock drivers are spe-
cifically designed for driving memory arrays requiring large
fanouts while operating at high speeds
This device meets the rise and fall time requirements of the
90 MHz and 100 MHz PentiumTM procrssors
The CGS2536 I O structures are CMOS The outputs are
separated into two banks of eight One bank consists of
divide by two outputs the other straight-through buffers
Within each bank half the outputs are inverting the other
half non-inverting
The CGS2536 specification guarantees part-to-part skew
variation
Features
Y Guaranteed
1 0 ns rise and fall times while driving 12 inches of
50X microstrip terminated with 25 pF
350 ps pin-to-pin skew (tOSLH and tOSHL)
Y 650 ps part-to-part variation on positive or negative
transition
Y Operates with either 3 3V or 5 0V supply
Y Inputs 5V tolerant with VCC in 3 3V range
Y Symmetric output current drive 24 mA IOH IOL
Y Industrial temperature of b40 C to a85 C
Y Symmetric package orientation
Y Large fanout for memory driving applications
Y Guaranteed 2 kV ESD protection
Y Implemented on National’s ABT family process
Y 28-pin PLCC for optimum skew performance
Connection Diagrams
Pin Assignment for 28-Pin PLCC
Truth Table
Input
In 0
In 1
In 2
In 3
Output
ABCD Out (0) d 2
ABCD Out (1) d 2
ABCD Out (2)
ABCD Out (3)
PentiumTM is a trademark of Intel Corporation
C1995 National Semiconductor Corporation TL F 12325
TL F 12325 – 1
CGS2536
TL F 12325 – 2
RRD-B30M105 Printed in U S A
1 page  
Power On Requirements
DETAILED DESCRIPTION
The divide by two block of the CGS2536 is accomplished
using two negative-edge-triggered flip-flops During power-
on the inverting flip-flop causes outputs Aout1 through
Dout1 to be High The non-inverting flip-flop causes outputs
Aout0 through Dout0 to be Low Two flip-flops are used to
achieve minimum skew between the non-inverting and in-
verting outputs
To guarantee that the flip-flops power-up out of phase the
IN0 and IN1 pins must be held low while power is applied to
VCC IN0 and IN1 must remain low until VCC t 3V
Application Hints
In a typical user environment IN0 and IN1 inputs may be
connected common Power is applied simultaneously to the
crystal oscillator and the CGS2536 If the oscillator output
does not deliver a clean first negative-going-edge to the IN0
and IN1 inputs only one flip-flop may toggle
Even if the user delays application of VCC to the CGS2536
a false trigger may occur Simply gating the oscillator to the
IN0 and IN1 inputs will not guarantee correct operation
since a ‘‘runt’’ pulse may propagate through the gate and
toggle only one of the flip-flops
Figure 1 shows a circuit that delivers ‘‘runt-free’’ negative-
going-edges to the IN0 and IN1 inputs This circuit ensures
that the first clocking pulse seen by the IN0 and IN1 inputs
consists of a full positive half-cycle of the crystal oscillator
Figure 2 shows the waveforms from the synchronizing cir-
cuit
The propagation delay of the 74AC00 gates and the toggle
frequency of the 74VHC164 limit the maximum frequency of
operation Equivalent logic elements that have faster propa-
gation delays can be substituted for the NAND gates and
shift register For example a generic GAL22V10-5 could be
programmed as the NAND gates that drive the CGS2536
Figure 1 CIRCUIT DESCRIPTION
Assumptions
1 VCC is applied simultaneously to the crystal oscillator
CGS2536 74AC00 and 74VHC164
2 A system power-on reset is ‘‘Low’’ long enough for VCC
and the crystal oscillator to stabilize
At power-on assertion (low) of the system power-on reset
clears the outputs of the 74VHC164 serial to parallel con-
verter
As a result nodes C and E are low ensuring power-on re-
quirements for the CGS2536 are met When the system
power-on reset is de-asserted the eighth positive-going-
edge received by the 74VHC164 causes node C to go high
Node C remains high as long as power is applied However
node D still remains high due to the oscillator output (A)
being low Node E stays low until the next positive-going-
edge of the oscillator Thus a full positive half-cycle of the
oscillator is seen by the IN1 and IN0 inputs which ensures
that both flip-flops of the divide by two toggle
TL F 12325 – 4
TL F 12325 – 5
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet CGS2536V.PDF ] | |
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