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PDF EN27LV020 Data sheet ( Hoja de datos )

Número de pieza EN27LV020
Descripción 2Megabit Low Voltage EPROM
Fabricantes EON 
Logotipo EON Logotipo



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No Preview Available ! EN27LV020 Hoja de datos, Descripción, Manual

EN27LV020 / EN27LV020B
EN27LV020 / EN27LV020B 2Megabit Low Voltage EPROM (256K x 8)
FEATURES
Read Access Time:
-90ns, -120ns, -150ns, -200ns
Single +3.3V Power Supply
-Regulated power supply 3.0V - 3.6V
(EN27LV020)
-Unregulated power supply 2.7V - 3.6V
(EN27LV020B for battery operated systems)
Programming Voltage +12.75V
QuikRiteTM Programming Algorithm
Typical programming time 20µs
Low Power CMOS Operation
1µA Standby (Typical)
15mA Operation (Max.)
CMOS- and TTL-Compatible I/O
High-Reliability CMOS Technology
Latch-Up Immunity to 100mA
from -1V to VCC + 1V
Two-Line Control ( OE & CE )
Standard Product Identification Code
JEDEC Standard Pinout
32-pin PDIP
32-pin PLCC
32-pin TSOP (Type 1)
Commercial and Industrial Temperature
Ranges
GENERAL DESCRIPTION
The EN27LV020 / EN27LV020B is a low-voltage, low-power 2-Megabit, 3.3V one-time-
programmable (OTP) read-only memory (EPROM). Organized into 256K words with 8 bits per
word, it features QuikRiteTM single-address location programming, typically at 20µs per byte. Any
byte can be accessed in less than 90ns. The EN27LV020 / EN27LV020B has separate Output
Enable ( OE ) and Chip Enable ( CE ) controls which eliminate bus contention issues. The
EN27LV020 has a Vcc tolerance range of 3.0V to 3.6 V, making it suitable for use in systems
that have regulated power supplies. The EN27LV020B has a Vcc tolerance range of 2.7 V to
3.6V, making it an ideal device for battery operated systems.
FIGURE 1. PDIP
Pin Name
A0-A17
DQ0-DQ7
CE
OE
PGM
Function
Addresses
Outputs
Chip Enable
Output Enable
Program Strobe
A17
4800 Great America Parkway Ste 202
Santa Clara, CA. 95054
1
Preliminary
Tel: 408-235-8680
Fax: 408-235-8685

1 page




EN27LV020 pdf
EN27LV020 / EN27LV020B
READ MODE
The EN27LV020 / EN27LV020B has two control functions, both of which must be logically
satisfied in order to obtain data at the outputs. Chip Enable ( CE ) is the power control and
should be used for device selection. Output Enable ( OE ) is the output control and should be
used to gate data to the output pins, independent of device selection. Assuming that
addresses are stable, address access time (tACC) is equal to the delay from CE to output
(tCE). Data is available at the outputs (tOE) after the falling edge of OE , assuming the CE
has been LOW and addresses have been stable for at least tACC - tOE.
STANDBY MODE
The EN27LV020 / EN27LV020B has CMOS standby mode which reduces the maximum VCC
current to 10µA. It is placed in CMOS standby when CE is at VCC ± 0.3 V. The EN27LV020
/ EN27LV020B also has a TTL-standby mode which reduces the maximum VCC current to 0.6
mA. It is placed in TTL-standby when CE is at VIH. When in standby mode, the outputs are
in a high-impedance state, independent of the OE input.
TWO-LINE OUTPUT CONTROL FUNCTION
To accommodate multiple memory connections, a two-line control function is provided to
allow for:
1. Low memory power dissipation,
2. Assurance that output bus contention will not occur.
It is recommended that CE be decoded and used as the primary device-selection function,
while OE be made a common connection to all devices in the array and connected to the
READ line from the system control bus. This assures that all deselected memory devices are in
their low-power standby mode and that the output pins are only active when data is desired
from a particular memory device.
SYSTEM CONSIDERATIONS
During the switch between active and standby conditions, transient current peaks are produced
on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks
is dependent on the output capacitance loading of the device. At a minimum, a 0.1µF ceramic
capacitor (high frequency, low inherent inductance) should be used on each device between
VCC and VSS to minimize transient effects. In addition, to overcome the voltage drop caused
by the inductive effects of the printed circuit board traces on EPROM arrays, a 4.7µF bulk
electrolytic capacitor should be used between VCC and VSS for each eight devices. The location
of the capacitor should be close to where the power supply is connected to the array.
4800 Great America Parkway Ste 202
Santa Clara, CA. 95054
5
Preliminary
Tel: 408-235-8680
Fax: 408-235-8685

5 Page





EN27LV020 arduino
EN27LV020 / EN27LV020B
FIGURE 8. PROGRAMMING WAVEFORMS
ADDRESS
DATA
VCC
VPP
CE
PGM
OE
VIH
VIL
VIH
VIL
6.5V
5.0V
PROGRAM
ADDRESS STABLE
tAS tOE
DATA IN
tDS
tDH
tVCS
13.0V
5.0V
tPRT
VIH
VIL
tVPS
tCES
VIH
VIL
tPW
VIH
VIL
tOES
READ
(VERIFY)
DATA OUT
VALID
tAH
tDFP
4800 Great America Parkway Ste 202
Santa Clara, CA. 95054
11
Preliminary
Tel: 408-235-8680
Fax: 408-235-8685

11 Page







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