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PDF EN27LN51208 Data sheet ( Hoja de datos )
| Número de pieza | EN27LN51208 | |
| Descripción | 3.3V NAND Flash Memory | |
| Fabricantes | EON | |
| Logotipo |  |
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EN27LN51208
EN27LN51208
512 Megabit (64 M x 8) SLC, 3.3 V NAND Flash Memory
1. Features
• Voltage Supply: 3.3V (2.7V ~ 3.6V )
• Organization
x 8:
- Memory Cell Array :
(64M + 2M) x 8bit
- Data Register : (2K + 64) x 8bit
• Automatic Program and Erase
x 8:
- Page Program : (2K + 64) Byte
- Block Erase : (128K + 4K) Byte
• Page Read Operation
- Page Size : (2K + 64) Byte (x 8)
- Random Read : 25µs (Max.)
- Serial Access : 25ns (Min.)
• Memory Cell: 1bit/Memory Cell
• Fast Write Cycle Time
- Page Program Time : 300µs (Typ.)
- Block Erase Time : 3ms (Typ.)
• Command/Address/Data Multiplexed I/O Port
• Hardware Data Protection
- Program/Erase Lockout During Power
Transitions
• Reliable CMOS Floating-Gate Technology
- ECC Requirement: x 8 - 4bit/512 Byte
- Endurance: 100K Program/Erase cycles
- Data Retention: 10 years
• Command Register Operation
• Automatic Page 0 Read at Power-Up Option
- Boot from NAND support
- Automatic Memory Download
• NOP: 4 cycles
• Cache Program Operation for High Performance
Program
• Cache Read Operation
• Copy-Back Operation
• EOD mode
• OTP Operation
• Bad-Block-Protect
• Commercial temperature Range
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. A, Issue Date: 2013/09/30
1 page  
5. Block Diagram
EN27LN51208
Figure 3. Functional Block Diagram (x8)
Figure 4. Array Organization (x8)
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. A, Issue Date: 2013/09/30
5 Page 
7.7 MODE SELECTION
EN27LN51208
CLE ALE CE# WE# RE#
WP#
Mode
H L L Rising H
L H L Rising H
X Read Mode Command Input
X Address Input (5 clock)
H L L Rising H
L H L Rising H
H
H
Write Mode
Command Input
Address Input (5 clock)
L L L Rising H
H Data Input
L
L
L
H Falling
X Data Output
XXXXH
X During Read (Busy)
XXXXX
H During Program (Busy)
XXXXX
H During Erase (Busy)
X X (1) X X X
L Write Protect
X X H X X 0V/VCC (2) Stand-by
Note:
1. X can be VIL or VIH.
2. WP# should be biased to CMOS high or CMOS low for stand-by.
7.8 Program / Erase Characteristics
(T =0 to 75℃, Vcc=2.7V ~ 3.6V)
A
Parameter
Symbol
Min.
Typ.
Max.
Unit
Average Program Time
Dummy Busy Time for Cache
Program
tPROG
tCBSY
-
300 750
us
- 3 750 us
Number of Partial Program Cycles
in the Same Page
NOP
- - 4 cycle
Block Erase Time
Dummy Busy Time for Two-Plane
Page Program
tBERS
TDBSY
- 3 10 ms
- 0.5 1 us
Note:
1. Typical program time is defined as the time within which more than 50% of the whole pages are
programmed at 3.3V VCC and 25°C temperature.
2. tPROG is the average program time of all pages. Users should be noted that the program
time variation from page to page is possible.
3. Max. time of tCBSY depends on timing between internal program completion and data in.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. A, Issue Date: 2013/09/30
11 Page | ||
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| PDF Descargar | [ Datasheet EN27LN51208.PDF ] | |
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