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PDF CBTL06141 Data sheet ( Hoja de datos )
| Número de pieza | CBTL06141 | |
| Descripción | Gen1 display 2 : 1 multiplexer | |
| Fabricantes | NXP Semiconductors | |
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CBTL06141
Gen1 display 2 : 1 multiplexer
Rev. 2 — 15 July 2010
Product data sheet
1. General description
The CBTL06141 is a six-channel (‘hex’) multiplexer for DisplayPort and PCI Express
applications at Generation 1 (‘Gen1’) speeds. It provides four differential channels
capable of 1 : 2 switching or 2 : 1 multiplexing (bidirectional and AC-coupled) PCI Express
or DisplayPort signals, using high-bandwidth pass-gate technology. Additionally, it
provides for switching/multiplexing of the Hot Plug Detect signal as well as the AUX or
DDC (Direct Display Control) signals, for a total of six channels on the display side. The
AUX and DDC channels provide a four-position multiplexer such that an additional level of
multiplexing can be accomplished when AUX and DDC I/Os are on separate pins of the
display source device.
The CBTL06141 is designed for Gen1 speeds, at 2.5 Gbit/s for PCI Express or 2.7 Gbit/s
for DisplayPort, and for inputs voltages of up to 3.3 V typical. It consumes very low current
in operational mode (less than 1 mA typical) and provides for a shutdown function (less
than 10 μA) to support battery-powered applications.
A typical application of CBTL06141 is on motherboards where one of two GPU display
sources needs to be selected to connect to a display sink device or connector. A controller
chip selects which path to use by setting a select signal HIGH or LOW. Due to the
non-directional nature of the signal paths (which use high-bandwidth passgate
technology), the CBTL06141 can also be used in the reverse topology, e.g., to connect
one display source device to one of two display sink devices or connectors.
Optionally, the hex MUX device can be used in conjunction with an HDMI/DVI level shifter
device (PTN3300A, PTN3300B or PTN3301) to allow for DisplayPort as well as HDMI/DVI
connectivity.
2. Features and benefits
1 : 2 switching or 2 : 1 multiplexing of DisplayPort (v1.1 - 2.7 Gbit/s) or PCI Express
(v1.1 - 2.5 Gbit/s) signals
4 high-speed differential channels with 2 : 1 muxing/switching for DisplayPort or
PCI Express signals
1 channel with 4 : 1 muxing/switching for AUX differential signals or DDC
single-ended clock and data signals
1 channel with 2 : 1 muxing/switching for single-ended HPD signals
High-bandwidth analog pass-gate technology
Very low intra-pair differential skew (< 5 ps)
Very low inter-pair skew (< 180 ps)
Switch/multiplexer position select CMOS input
Shutdown mode CMOS input
1 page  
NXP Semiconductors
CBTL06141
Gen1 display 2 : 1 multiplexer
6.2 Pin description
Table 2. Pin description
Symbol
Ball Type
GPU_SEL
A1 3.3 V low-voltage CMOS
single-ended input
DDC_AUX_SEL C2
3.3 V low-voltage CMOS
single-ended input
XSD
TST0
DIN1_0+
DIN1_0−
DIN1_1+
DIN1_1−
DIN1_2+
DIN1_2−
DIN1_3+
DIN1_3−
DIN2_0+
DIN2_0−
DIN2_1+
DIN2_1−
DIN2_2+
DIN2_2−
DIN2_3+
DIN2_3−
DOUT_0+
DOUT_0−
DOUT_1+
DOUT_1−
DOUT_2+
DOUT_2−
DOUT_3+
DOUT_3−
DAUX1+
DAUX1−
DAUX2+
DAUX2−
B7 3.3 V low-voltage CMOS
single-ended input
G2 3.3 V low-voltage CMOS
single-ended input
B4 differential I/O
A4 differential I/O
B5 differential I/O
A5 differential I/O
B6 differential I/O
A6 differential I/O
A8 differential I/O
A9 differential I/O
B8 differential I/O
B9 differential I/O
D8 differential I/O
D9 differential I/O
E8 differential I/O
E9 differential I/O
F8 differential I/O
F9 differential I/O
B2 differential I/O
B1 differential I/O
D2 differential I/O
D1 differential I/O
E2 differential I/O
E1 differential I/O
F2 differential I/O
F1 differential I/O
H9 differential I/O
J9 differential I/O
H6 differential I/O
J6 differential I/O
Description
Selects between two multiplexer/switch paths. When HIGH, path 2
left-side is connected to its corresponding right-side I/O. When
LOW, path 1 left-side is connected to its corresponding right-side
I/O.
Selects between DDC and AUX paths. When HIGH, the CLK and
DAT I/Os are connected to their respective DDCOUT terminals.
When LOW, the AUX+ and AUX− I/Os are connected to their
respective DDCOUT terminals.
Shutdown pin. Should be driven HIGH or connected to VDD for
normal operation. When LOW, all paths are switched off
(non-conducting) and supply current consumption is minimized.
Test pin for NXP use only. Should be tied to ground in normal
operation.
Four high-speed differential pairs for DisplayPort or PCI Express
signals, path 1, left-side.
Four high-speed differential pairs for DisplayPort or PCI Express
signals, path 2, left-side.
Four high-speed differential pairs for DisplayPort or PCI Express
signals, right-side.
High-speed differential pair for AUX signals, path 1, left-side.
High-speed differential pair for AUX signals, path 2, left-side.
CBTL06141
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 15 July 2010
© NXP B.V. 2010. All rights reserved.
5 of 18
5 Page 
NXP Semiconductors
CBTL06141
Gen1 display 2 : 1 multiplexer
11. Application information
11.1 Special considerations
Certain cable or dongle misplug scenarios make it possible for a 5 V input condition to
occur on pins AUX+ and AUX−, as well as HPDIN. When AUX+ and AUX− are connected
through a minimum of 2.2 kΩ each, the CBTL06141 will sink current but will not be
damaged. Similarly, HPDIN may be connected to 5 V via at least a 1 kΩ resistor. (Correct
functional operation to specification is not expected in these scenarios.) The latter also
prevents the HPDIN input from loading down the system HPD signal when power to the
CBTL06141 is off.
CBTL06141
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 15 July 2010
© NXP B.V. 2010. All rights reserved.
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