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Número de pieza PCE85176AUG
Descripción 4 x 40 LCD segment driver
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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PCE85176AUG
4 × 40 LCD segment driver for Chip-On-Glass
Rev. 1 — 12 January 2015
Product data sheet
1. General description
The PCE85176AUG is a peripheral device which interfaces to almost any Liquid Crystal
Display (LCD)1 with low multiplex rates. It generates the drive signals for any static or
multiplexed LCD containing up to four backplanes and up to 40 segments. The
PCE85176AUG is compatible with most microcontrollers and communicates via the
two-line bidirectional I2C-bus. Communication overheads are minimized by a display RAM
with auto-incremented addressing and by display memory switching (static and duplex
drive modes).
For a selection of NXP LCD segment drivers, see Table 31 on page 40.
2. Features and benefits
Single chip LCD controller and driver
Selectable backplane drive configuration: static, 2, 3, or 4 backplane multiplexing
Selectable display bias configuration: static, 12, or 13
Internal LCD bias generation with voltage-follower buffers
40 segment drives:
Up to 20 7-segment alphanumeric characters
Up to 10 14-segment alphanumeric characters
Any graphics of up to 160 elements
40 4-bit RAM for display data storage
Display memory bank switching in static and duplex drive modes
Versatile blinking modes
Independent supplies possible for LCD and logic voltages
Wide power supply range: from 1.8 V to 5.5 V
Wide logic LCD supply range:
From 2.5 V for low-threshold LCDs
Up to 5.5 V for high-threshold twisted nematic LCDs
Low power consumption
400 kHz I2C-bus interface
No external components required
Compatible with Chip-On-Glass (COG) technology
1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 19.

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PCE85176AUG pdf
NXP Semiconductors
PCE85176AUG
4 × 40 LCD segment driver for Chip-On-Glass
7.1.1 Command: mode-set
The mode-set command allows configuring the multiplex mode, the bias levels and
enabling or disabling the display.
Table 7. Mode-set command bit allocation
Bit position labeled as - is not used.
Bit 7 6 5 4 3 2 1 0
Symbol
C
1
0
-
EB
M[1:0]
Table 8. Mode-set command bit description
Bit position labeled as - is not used.
Bit Symbol
Value
7C
0, 1
6, 5 -
10
4-
-
3E
0
1
2B
0
1
1 to 0 M[1:0]
01
10
11
00
Description
see Table 6
fixed value
unused
display status[1]
disabled (blank)[2]
enabled
LCD bias configuration[3]
13 bias
12 bias
LCD drive mode selection
static; BP0
1:2 multiplex; BP0, BP1
1:3 multiplex; BP0, BP1, BP2
1:4 multiplex; BP0, BP1, BP2, BP3
[1] The possibility to disable the display allows implementation of blinking under external control.
[2] The display is disabled by setting all backplane and segment outputs to VLCD.
[3] Not applicable for static drive mode.
7.1.2 Command: load-data-pointer
The load-data-pointer command defines the display RAM address where the following
display data is sent to.
Table 9. Load-data-pointer command bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol
C
0
P[5:0]
Table 10. Load-data-pointer command bit description
See Section 7.3.1.
Bit Symbol
Value
Description
7C
0, 1 see Table 6
6 0 0 fixed value
5 to 0 P[5:0]
000000 to
10 0111
6-bit binary value, 0 to 39; transferred to
the data pointer to define one of 40 display
RAM addresses
PCE85176AUG
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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PCE85176AUG arduino
NXP Semiconductors
PCE85176AUG
4 × 40 LCD segment driver for Chip-On-Glass
7.3.1 Writing to RAM
The addressing mechanism for the display RAM is realized using the data pointer. This
allows the loading of an individual display data byte, or a series of display data bytes, into
any location of the display RAM.
The sequence always commences with the initialize-RAM command (see Table 12).
Following this command, the data pointer has to be set to the desired RAM address using
the load-data-pointer command (see Table 10). After this an arriving data byte is stored at
the display RAM address indicated by the data pointer. The RAM writing procedure is
illustrated in Figure 5 and the filling order of the RAM is shown in Figure 4.
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Fig 5. RAM writing procedure
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After each byte is stored, the content of the data pointer is automatically incremented by a
value dependent on the selected LCD drive mode:
In static drive mode by eight.
In 1:2 multiplex drive mode by four.
In 1:3 multiplex drive mode by three.
In 1:4 multiplex drive mode by two.
If an I2C-bus data access terminates early, then the state of the data pointer is unknown.
So, the data pointer must be rewritten before further RAM accesses.
PCE85176AUG
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
11 of 48

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