PDF CDP1878C Data sheet ( Hoja de datos )

Número de pieza	CDP1878C
Descripción	CMOS Dual Counter-Timer
Fabricantes	Intersil Corporation
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No Preview Available ! CDP1878C March 1997 CMOS Dual Counter-Timer Features • Compatible with General Purpose and CDP1800 Series Microprocessor Systems • Two 16-Bit Down Counters and Two 8-Bit Control Registers • 5 Modes Including a Versatile Variable-Duty Cycle Mode • Programmable Gate-Level Select • Two-Complemented Output Pins for Each Counter- Timer • Software-Controlled Interrupt Output • Addressable in Memory Space or CDP1800-Series I/O Space Ordering Information PART NUMBER CDP1878CE CDP1878CD TEMP. RANGE PACKAGE -40oC to +85oC PDIP -40oC to +85oC SBDIP PKG. NO. E28.6 N28.6 Description The CDP1878C is a dual counter-timer consisting of two 16- bit programmable down counters that are independently controlled by separate control registers. The value in the reg- isters determine the mode of operation and control func- tions. Counters and registers are directly addressable in memory space by any general industry type microproces- sors, in addition to input/output mapping with the CDP1800 series microprocessors. Each counter-timer can be conﬁgured in ﬁve modes with the additional ﬂexibility of gate-level control. The control regis- ters in addition to mode formatting, allow software start and stop, interrupt enable, and an optional read control that allows a stable readout from the counters. Each counter- timer has software control of a common interrupt output with an interrupt status register indicating which counter-timer has timed out. In addition to the interrupt output, true and complemented outputs are provided for each counter-timer for control of peripheral devices. This type is supplied in 28-lead dual-in-line ceramic pack- ages (D sufﬁx), and 28-lead dual-in-line plastic packages (E sufﬁx). Pinout CDP1878C (DIP) TOP VIEW INT 1 TAO 2 TAO 3 TAG 4 TACL 5 RD 6 IO/MEM 7 TPB/WR 8 TPA 9 CS 10 A0 11 A1 12 A2 13 VSS 14 28 VDD 27 DB7 26 DB6 25 DB5 24 DB4 23 DB3 22 DB2 21 DB1 20 DB0 19 TBO 18 TBO 17 TBG 16 TBCL 15 RESET TABLE 1. MODE DESCRIPTION MODE FUNCTION APPLICATION 1 Timeout Outputs change when clock Event counter decrements counter to “0” 2 Timeout Strobe One clockwide output pulse when clock decrements counter to “0” Trigger pulse 3 Gate-Con- trolled One Shot Outputs change when clock decrements counter to “0”. Retriggerable Time-delay generation 4 Rate Generator Repetitive clockwide output Time-base pulse generator 5 Variable-Duty Repetitive output with Cycle programmed duty cycle Motor control CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 \| Copyright © Intersil Corporation 1999 4-91 File Number 1341.2 1 page CDP1878C Functional DescriptIon The dual counter-timer consists of two programmable 16-bit down counters, separately addressable and controlled by two independent 8-bit control registers. The word in the con- trol register determines the mode and type of operation that the counter-timer performs. Writing to or reading from a counter or register is enabled by selective addressing during a write or read cycle. The data is placed on the data bus by the microprocessor during the write cycle or read from the counter during the read cycle. Data to and from the counters and to the control registers is in binary format. Each counter-timer consists of three parts. The ﬁrst is the counter itself, a 16-bit down counter that is decremented on the trailing edge of the clock input. The second is the jam register that receives the data when the counter is written to. The word in the control register determines when the jam register value is placed into the counter. The third part is the holding register that places the counter value on the data bus when the counter is read. When the counter has decremented to zero, three events occur. The ﬁrst involves the common interrupt output pin that, if enabled, becomes active low. The second is the setting of a bit in the interrupt status register. This register can be read to determine which counter-timer has timed out. The third event is the logic change of the complemented output pins. In addition to the clock input used to decrement the counter, a gate input is available to enable or initiate operation. The counter-timers are independent and can have different mode operations. Write Operation The counters and registers are separately addressable and are programmed via the data bus when the chip is selected with the TPB/WR pin active. Normal sequencing requires that the counter jam register be loaded ﬁrst with the required value (most signiﬁcant and least signiﬁcant byte in any order), and then the control register be accessed and loaded with the control word. The trailing edge of the TPB/WR pulse will latch the control word into the control register. The trailing edge of the ﬁrst clock to occur with gate valid will cause the counter to be jammed with its initial value. The counter will decrement on the trailing edge of succeeding clocks as long as the gate is valid, until it reaches zero. The output levels will then change, and if enabled, the interrupt output will become active and the appropriate timer bit will be set in the interrupt status register. The interrupt output and the interrupt status register can be cleared (to their inactive state) by addressing the control reg- ister with the TPB/WR line active For example, if counter A times out, control register A must be accessed to reset the interrupt output high and reset the timer A bit in the status reg- ister low. Timer B bit in the status register will be unaffected. Read Operation Each counter has a holding register that is continuously being updated by the counter and is accessed when the counter is addressed during read cycles. Counter reads are accomplished by halting the holding register and then read- ing it, or by reading the holding register directly. If the holding register is read directly, data will appear on the bus if the counters are addressed with the RD line active. However, if the clock decrements the counter between the two read operations (most and least signiﬁcant byte), an inaccurate value will be read. To preclude this from happening, writing a “1” into bit 6 of the control register and then addressing and reading the counter will result in a stable reading. This oper- ation prevents the holding register from being updated by the counter and does not affect the counter’s operation. The interrupt status register is read by addressing either control register with the RD line active. A “1” in bit 7 indicates Timer A has timed out and a “1” in bit 6 indicates Timer B has timed out. Bits 0-5 are zeros. Control Register 76543210 JAM ENABLE 1 = ENABLE 0 = DISABLE HOLDING REGISTER CONTROL 1 = FREEZE HOLDING REGISTER 0 = UPDATE CONTINUOUSLY START/STOP CONTROL 1 = START COUNTER 0 = STOP COUNTER GATE LEVEL SELECT 1 = POSITIVE (HIGH) 0 = NEGATIVE (LOW) INTERRUPT ENABLE 1 = ENABLE 0 = DISABLE MODE SELECT 001 = MODE 1 010 = MODE 2 †011 = MODE 3 100 = MODE 4 101 = MODE 5 †PLUS BIT 7 = 0 Bits 0, 1 and 2 Mode Selects - See Mode Timing Diagrams (Figures 1, 2, 3, 4, and 5). Note: When selecting a mode, the timer outputs TAO and TBO are set low, and TAO and TBO are set high. If bits 0, 1 and 2 are all zero’s when the control register is loaded, no mode is selected, and the counter-timer outputs are unaffected. Issuing mode 6 will cause an indeterminate condition of the counter, issuing mode 7 is equivalent to issuing mode 5. BIT 7 BIT 2 BIT 1 BIT 0 Mode 1 - Timeout - 001 Mode 2 - Timeout Strobe - 010 Mode 3 - Gate Controlled One Shot 0 0 1 1 Mode 4 - Rate Generator - 100 Mode 5 - Variable-Duty Cycle - 101 No Mode selected. Counter outputs - 0 0 0 unaffected 4-95 5 Page CDP1878C MEMORY CLOCK XTAL ADDRESS LINES CLEAR TPA MRD TPB N0 N1 N2 INT CDP1802 VDD TACL, TBCL RESET TPA RD TPB/WR A0 A1 A2 CS IO/MEM INT COUNTER - TIMER DB0 - DB7 TAG GATE INPUTS TBG TAO TAO TIMER OUTPUTS TBO TBO DATA BUS FIGURE 11. TYPICAL CDP1802 INPUT/OUTPUT-MAPPED SYSTEM TPA RD N LINES TPB/WR DATA LATCHED DATA FROM MEMORY TO COUNTER-TIMER VALID DATA FIGURE 12. CDP1800-SERIES INPUT/OUTPUT-MAPPING TIMING WAVEFORMS WITH OUTPUT INSTRUCTION TPA OUTPUT DRIVERS ENABLED RD TPB/WR OUTPUT DRIVERS DISABLED N LINES DATA FROM COUNTER-TIMER TO MEMORY VALID DATA FIGURE 13. CDP1800-SERIES INPUT/OUTPUT-MAPPING TIMING WAVEFORMS WITH INPUT INSTRUCTION 4-101 11 Page

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