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PDF CDP1871AC Data sheet ( Hoja de datos )

Número de pieza CDP1871AC
Descripción CMOS Keyboard Encoder
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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No Preview Available ! CDP1871AC Hoja de datos, Descripción, Manual

REFERENCE APP NOTE 7374
August 1996
CDP1871A,
CDP1871AC
CMOS Keyboard Encoder
Features
• Directly Interfaces with CDP1800-Series Microprocessor
• Low Power Dissipation
• Three-State Outputs
• Scans and Generates Code for 53 Key ASCII Keyboard Plus
32 HEX Keys (SPST Mechanical Contact Switches)
• Shift, Control, and Alpha Lock Input
• RC-Controlled Debounce Circuitry
• Single Supply 4V to 10.5V . . . . . . . . . . . . . (CDP1871A)
4V to 6.5V . . . . . . . . . . . . . (CDP1871AC)
• N-Key Lockout
Ordering Information
PACKAGE
PDIP
PLCC
SBDIP
TEMP. RANGE
5V
-40oC to +85oC CDP1871ACE
-40oC to +85oC CDP1871ACQ
-40oC to +85oC CDP1871ACD
PKG.
10V NO.
CDP1871AE E40.6
- N44.65
CDP1871AD D40.6
Burn-In
CDP1871ACDX
- D40.6
Description
The CDP1871A is a keyboard encoder designed to
directly interface between a CDP1800-series micro-
processor and a mechanical keyboard array, providing
up to 53 ASCII coded keys and 32 HEX coded keys,
as shown in the system diagram (Figure 1).
The keyboard may consist of simple single-pole
single-throw (SPST) mechanical switches. Inputs are
provided for alpha-lock, control, and shift functions,
allowing 160 unique codes. An external R-C input is
available for user-selectable debounce times. The N-
key lock-out feature prevents unwanted key codes if
two or more keys are pressed simultaneously.
The CDP1871A and CDP1871AC are functionally
identical. They differ in that the CDP1871A has a
recommended operating voltage range of 4V to 10.5V,
and the CDP1871AC has a recommended operating
voltage range 4V to 6.5V. These types are supplied in
40 lead dual-in-line ceramic packages (D suffix), and
40 lead dual-in-line plastic packages (E suffix), and 44
lead plastic chip-carrier packages (Q suffix).
Pinouts
40 LEAD PDIP, CERDIP
TOP VIEW
D1 1
D2 2
D3 3
D4 4
D5 5
D6 6
D7 7
D8 8
D9 9
D10 10
D11 11
S1 12
S2 13
S3 14
S4 15
S5 16
S6 17
S7 18
S8 19
VSS 20
40 VDD
39 SHIFT
38 CONTROL
37 ALPHA
36 DEBOUNCE
35 RTP
34 TPB
33 DA
32 BUS 7
31 BUS 6
30 BUS 5
29 BUS 4
28 BUS 3
27 BUS 2
26 BUS 1
25 BUS 0
24 CS4
23 CS3
22 CS2
21 CS1
44 LEAD PLCC
(Q Suffix) TOP VIEW
6 5 4 3 2 1 44 43 42 41 40
D5 7
D6 8
D7 9
D8 10
D9 11
D10 12
D11 13
S1 14
S2 15
S3 16
S4 17
39
38
37
36
35
34
33
32
31
30
29
18 19 20 21 22 23 24 25 26 27 28
RPT
TPB
DA
BUS 7
BUS 6
BUS 5
BUS 4
BUS 3
BUS 2
BUS 1
NC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-66
File Number 1374.2

1 page




CDP1871AC pdf
CDP1871A, CDP1871AC
Functional Description of
CDP1871A Terminals
D1 - D11 (Outputs):
Drive lines for the 11 x 8 keyboard switch matrix. These
outputs are connected through the external switch matrix to
the sense lines (S1 - S8).
TPB (Input):
The input clock used to drive the scan generator and reset
the status flag (DA). This input is normally connected to the
TPB output of the CDP1800-series microprocessor.
S1 - S8 (Inputs):
Sense lines for the 11 x 8 keyboard maxtrix. These inputs
have internal pull-down resistors and are driven high by
appropriate drive line when a keyboard switch is closed.
CS1, CS2, CS3, CS4 (Inputs):
Chip select inputs, which are used to enable the three-state
data bus outputs (BUS 0 - BUS 7) and to enable the reset-
ting of the status flag (DA), which occurs on the low-to-high
transition of TPB. These four inputs are normally connected
to the N-lines (N0-N2) and MRD output of the CDP1800-
series microprocessor. (Table 2)
BUS 0 - BUS 7 (Outputs):
Three-state data bus outputs which provide the ASCll and
HEX codes of the detected keys. The outputs are normally
connected to the BUS 0 - BUS 7 terminals of the CDP1800-
series microprocessor.
DA (Output):
The data available output flag which is set low when a valid
key closure is detected. It is reset high by the low-to-high
transition of TPB when data is read from the CDP1871A.
This output is normally connected to a flag input (EF1 - EF4)
of the CDP1800-series microprocessor.
RPT (Output):
The repeat output flag which is used to indicate that a key is
still closed after data has been read from the CDP1871A
(DA = high). It remains low as long as the key is closed and
is used for an autorepeat function, under CPU control. This
output is normally connected to a flag input (EF1 - EF4) of
the CDP1800-series microprocessor.
DEBOUNCE (Input):
This input is connected to the junction of an external resistor
to VDD and capacitor to VSS. It provides a debounce time
delay (t RC) after the release of a key. If a debounce is not
desired, the external pull-up resistor is still required.
ALPHA, SHIFT, CONTROL (Inputs):
A high on the SHIFT or CONTROL inputs will be internally
latched (after the debounce time) and the drive and sense
line decoding will be modified as shown in Table 3. They are
normally connected to the keyboard, but produce no code by
themselves. The SHIFT and CONTROL inputs have internal
pull-down resistors to simplify use with momentary contact
switches. The ALPHA input is not latched and is designed for
a standard SPDT switch to provide an alpha-lock function.
When ALPHA = 1 the drive and sense line decoding will be
modified as shown in Table 3.
VDD, VSS:
VDD is the positive supply voltage input. VSS is the most
negative supply voltage terminal and is normal connected to
ground. All outputs swing from VSS to VDD. The
recommended input voltage swing is from VSS to VDD.
CONTROL
0
1
0
0
NOTE: X = Don’t Care
TABLE 1. SWITCH INPUT FUNCTIONS
SHIFT
0
X
1
0
ALPHA
0
X
X
1
KEY FUNCTION
Normal
Control
Shift
Alpha
4-70

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