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PDF CDP1854AC Data sheet ( Hoja de datos )

Número de pieza CDP1854AC
Descripción Programmable Universal Asynchronous Receiver/Transmitter (UART)
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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No Preview Available ! CDP1854AC Hoja de datos, Descripción, Manual

March 1997
CDP1854A,
CDP1854AC
Programmable Universal Asynchronous
Receiver/Transmitter (UART)
Features
Description
• Two Operating Modes
- Mode 0 - Functionally Compatible with Industry
Types Such as the TR1602A and CDP6402
- Mode 1 - Interfaces Directly with CDP1800-Series
Microprocessors without Additional Components
• Full or Half Duplex Operation
• Parity, Framing and Overrun Error Detection
• Baud Rate
- DC to 200K Bits/s at VDD . . . . . . . . . . . . . . . . . . . . 5V
- DC to 400K Bits/s at VDD . . . . . . . . . . . . . . . . . . . . 10V
• Fully Programmable with Externally Selectable Word
Length (5-8 Bits), Parity Inhibit, Even/Odd Parity, and
1, 1-1/2, or 2 Stop Bits
• False Start Bit Detection
Ordering Information
The CDP1854A and CDP1854AC are silicon-gate CMOS
Universal Asynchronous Receiver/Transmitter (UART) cir-
cuits. They are designed to provide the necessary formatting
and control for interfacing between serial and parallel data.
For example, these UARTs can be used to interface between
a peripheral or terminal with serial I/O ports and the 8-bit
CDP1800-series microprocessor parallel data bus system.
The CDP1854A is capable of full duplex operation, i.e.,
simultaneous conversion of serial input data to parallel out-
put data and parallel input data to serial output data.
The CDP1854A UART can be programmed to operate in one
of two modes by using the mode control input. When the
input is high (MODE = 1), the CDP1854A is directly compati-
ble with the CDP1800-series microprocessor system without
additional interface circuitry. When the mode input is low
(MODE = 0), the device is functionally compatible with indus-
try standard UART’s such as the TR1602A and CDP6402. It
is also pin compatible with these types, except that pin 2 is
used for the mode control input.
TEMP.
PACKAGE RANGE
5V/200K
BAUD
PDIP
-40oC to +85oC CDP1854ACE
10V/400K PKG.
BAUD
NO.
CDP1854AE E40.6
Burn-In
PLCC
SBDIP
CDP1854ACEX
-40oC to +85oC CDP1854ACQ
-40oC to +85oC CDP1854ACD
CDP1854AEX
CDP1854AQ
CDP1854AD
E40.6
N44.65
D40.6
Burn-In
CDP1854ACDX
- D40.6
The CDP1854A and the CDP1854AC are functionally identi-
cal. The CDP1854A has a recommended operating voltage
range of 4V to 10.5V, and the CDP1854AC has a recom-
mended operating voltage range of 4V to 6.5V.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
5-42
File Number 1193.2

1 page




CDP1854AC pdf
CDP1854A, CDP1854AC
Static Electrical Specifications at TA = -40oC to +85oC, Unless Otherwise Noted (Continued)
CONDITIONS
LIMITS
CDP1854A
CDP1854AC
PARAMETER
VO VIN VDD
(NOTE 1)
(NOTE 1)
(V) (V) (V) MIN TYP MAX MIN TYP MAX UNITS
Three-State Output
Leakage Current
IOUT
0, 5
0, 10
0, 5
0, 10
5
10
-
-
- ±1 -
- ±10 -
- ±1 µA
- - µA
Operating Current
IDD1
- 0, 5 5
-
1.5
-
(Note 3)
- 0, 10 10 - 6 -
- 1.5
--
- mA
- mA
Input Capacitance
CIN
-
--
-
5 7.5 -
5 7.5 pF
Output Capacitance COUT
-
--
-
10 15 -
10
15 pF
NOTES:
1. Typical values are for TA = 25oC.
2. IOL = IOH = 1µA.
3. Operating current is measured at 200kHz or VDD = 5V and 400kHz for VDD = 10V in a CDP1800-series microprocessor system, with
open outputs.
Operating Conditions At TA = Full Package-Temperature Range. For maximum reliability, operating conditions should be selected so
that operation is always within the following ranges:
PARAMETER
DC Operating Voltage Range
Input Voltage Range
Baud Rate (Receive or Transmit)
CONDITIONS
VDD
(V)
-
-
5
10
CDP1854A
MIN MAX
4 10.5
VSS
-
VDD
200
- 400
LIMITS
CDP1854AC
MIN MAX
4 6.5
VSS
-
VDD
200
--
UNITS
V
V
K bits/s
K bits/s
5-46

5 Page





CDP1854AC arduino
CDP1854A, CDP1854AC
Dynamic Electrical Specifications TA = -40oC to +85oC, VDD ±5%, tR, tF = 20ns, VIH = 0.7 VDD, VIL = 0.3 VDD, CL = 100pF,
(See Figure 4)
LIMITS
CDP1854A
CDP1854AC
PARAMETER
VDD (NOTE 1) (NOTE 2) (NOTE 1) (NOTE 2)
(V)
TYP
MAX
TYP
MAX
UNITS
RECEIVER TIMING - MODE 1
Minimum Clock Period
tCC 5
10
250 310 250 310
125 155
-
-
ns
ns
Minimum Pulse Width
Clock Low Level
tCL 5
10
100 125 100 125
75 100
-
-
ns
ns
Clock High Level
tCH 5
10
100 125 100 125
75 100
-
-
ns
ns
TPB
tTT 5
100 150 100 150
ns
10 50 75
-
- ns
Minimum Setup Time
Data Start Bit to Clock
tDC 5
10
100 150 100 150
50 75
-
-
ns
ns
Propagation Delay Time
TPB to DATA AVAILABLE
tTDA
5
10
220 325 220 325
110 175
-
-
ns
ns
Clock to DATA AVAILABLE
tCDA
5
10
220 325 220 325
110 175
-
-
ns
ns
Clock to Overrun Error
tCOE
5
10
210 300 210 300
105 150
-
-
ns
ns
Clock to Parity Error
tCPE
5
10
240 375 240 375
120 175
-
-
ns
ns
Clock to Framing Error
tCFE
5
10
200 300 200 300
100 150
-
-
ns
ns
NOTES:
1. Typical values for TA = 25oC and nominal voltages.
2. Maximum limits of minimum characteristics are the values above which all devices function.
5-52

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