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PDF CDP1852C Data sheet ( Hoja de datos )
| Número de pieza | CDP1852C | |
| Descripción | Byte-Wide Input/Output Port | |
| Fabricantes | Intersil Corporation | |
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TM CDP1852,
CDP1852C
March 1997
Byte-Wide Input/Output Port
Features
• Static Silicon-Gate CMOS Circuitry
• Parallel 8-Bit Data Register and Buffer
• Handshaking Via Service Request Flip-Flop
• Low Quiescent and Operating Power
• Interfaces Directly with CDP1800-Series
Microprocessors
• Single Voltage Supply
• Full Military Temperature Range (-55oC to +125oC)
Ordering Information
PACKAGE
PDIP
SBDIP
TEMP. RANGE
5V
10V
-40oC to +85oC CDP1852CE CDP1852E
-40oC to +85oC CDP1852CD CDP1852D
PKG.
NO.
E24.6
D24.6
Description
The CDP1852 and CDP1852C are parallel, 8-bit, mode-pro-
grammable input/output ports. They are compatible and will
interface directly with CDP1800-series microprocessors. They
are also useful as 8-bit address latches when used with the
CDP1800 multiplexed address bus and as I/O ports in general-
purpose applications.
The mode control is used to program the device as an input port
(mode = 0) or as an output port (mode = 1). The SR/SR output
can be used as a signal to indicate when data is ready to be
transferred. In the input mode, a peripheral device can strobe
data into the CDP1852, and microprocessor can read that data
by device selection. In the output mode, a microprocessor
strobes data into the CDP1852, and handshaking is established
with a peripheral device when the CDP1852 is deselected.
In the input mode, data at the data-in terminals (DI0-DI7) is
strobed into the port’s 8-bit register by a high (1) level on the
clock line. The negative high-to-low transition of the clock
latches the data in the register and sets the service request out-
put low (SR/SR = 0). When CS1/CS1 and CS2 are high
(CS1/CS1 and CS2 = 1), the three-state output drivers are
enabled and data in the 8-bit register appear at the data-out ter-
minals (D00-D07). When either CS1/CS1 or CS2 goes low
(CS1/CS1 or CS2 = 0), the data-out terminals are three-stated
and the service request output returns high (SR/SR =1).
In the output mode, the output drivers are enabled at all times.
Data at the data-in terminals (DI0-DI7) is strobed into the 8-bit
register when CS1/CS1 is low (CS1/CS1 = 0) and CS2 and the
clock are high (1), and are present at the data-out terminals
(D00-D07). The negative high-to-low transition of the clock
latches the data in the register. The SR/SR output goes high
(SR/SR = 1) when the device is deselected (CS1/CS1 = 1 or
CS2 = 0) and returns low (SR/SR = 0) on the following trailing
edge of the clock.
Pinout
24 LEAD DIP
TOP VIEW
Typical CDP1802 Microprocessor System
CSI/CSI 1
MODE 2
DI0 3
DO0 4
DI1 5
DO1 6
DI2 7
DO2 8
DI3 9
DO3 10
CLOCK 11
VSS 12
24 VDD
23 SR/SR
22 DI7
21 DO7
20 DI6
19 DO6
18 DI5
17 DO5
16 DI4
15 DO4
14 CLEAR
13 CS2
ROM
ADDR BUS
TPA
MRD
CEO
RAM
ADDR BUS
TPA
CPU
CDP1802
MRD
MWR
N0 - N2 MRD
TPB
Q
SC0 SC1
INTERRUPT
I/O
CDP1852
DMA - IN DMA - OUT
EF1 - EF4
DATA
CONTROL
BIDIRECTIONAL DATA BUS
FIGURE 1.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1
File Number 1166.2
1 page  
CDP1852, CDP1852C
Dynamic Electrical Specifications At TA = -40oC to +85oC, VDD = ±5%, tR, tF = 20ns, VIH = 0.7 VDD, VIL = 0.3 VDD, CL = 100pF,
and 1 TTL Load (Continued)
LIMITS
PARAMETER
VDD (NOTE 1)
(V)
MIN
TYP
MAX
UNITS
Minimum Data Setup Time
tDS 5
- -10 0 ns
10 - -5 0 ns
Minimum Data Hold Time
tDH 5
- 75 150 ns
10 - 35 75 ns
Data Out Hold Time (Note 2)
tDOH
5
10
30 185 370 ns
15 100 200 ns
Propagation Delay Times, tPLH, tPHL
Select to Data Out (Note 2)
tSDO
5
10
30 185 370 ns
15 100 200 ns
Clear to SR
tRSR
5
10
-
170 340
ns
- 85 170 ns
Clock to SR
tCSR
5
10
-
110 220
ns
- 55 110 ns
Select to SR
tSSR
5
10
-
120 240
ns
- 60 120 ns
NOTES:
1. Typical values are for TA = 25oC and nominal VDD.
2. Minimum value is measured from CS2, maximum value is measured from CS1/CS1.
Input Port Mode 0 - Typical Operation
General Operation
When the mode control is tied to VSS, the CDP1852
becomes an input port. In this mode, the peripheral device
places data into the CDP1852 with a strobe pulse and the
CDP1852 signals the microprocessor that data is ready to be
transferred on the strobe’s trailing edge via the SR output
line. The CDP1802 then issues an input instruction that
enables the CDP1852 to place the information from the
peripheral device on the data bus to be entered into a mem-
ory location and the accumulator of the microprocessor.
Detailed Operation (See Figure 5)
The STROBE from the peripheral device places DATA into
the 8-bit register of the CDP1852 when it goes high and
latches the DATA on its trailing edge. The SR output is set
low on the strobe’s trailing edge. This output is connected to
a flag line of the CDP1802 microprocessor and software poll-
ing will determine that the flag line has gone low and periph-
eral data is ready to be transferred. The CDP1802 then
issues an input instruction that places an NX line high. With
the MRD line also high, the CDP1852 is selected and its out-
put drivers place the DATA from the peripheral device on the
DATA BUS. When the CDP1802 selected the CDP1852, it
also selected and addressed the memory via one of the 16
internal address registers selected by an internal “X” regis-
ter. The data from the CDP1852 is therefore entered into the
memory [Bus → M(R(X))]. The data is also transferred to the
D register (accumulator) in the microprocessor (Bus → D).
When the CDP1802’s execute cycle is completed, the
CDP1852 is deselected by the NX line returning low and its
data output pins are three-stated. The SR output returns
high.
5
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