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PDF CDP1851C Data sheet ( Hoja de datos )
| Número de pieza | CDP1851C | |
| Descripción | CMOS Programmable I/O Interface | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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CDP1851,
CDP1851C
March 1997
CMOS Programmable I/O Interface
Features
• 20 Programmable I/O Lines
• Programmable for Operation in Four Modes:
- Input
- Output
- Bidirectional
- Bit-programmable
• Operates in Either I/O or Memory Space
Ordering Information
PACKAGE TEMP. RANGE
5V
PKG.
10V NO.
PDIP
-40oC to +85oC CDP1851CE CDP1851E E40.6
Burn-In
CDP1851CEX - E40.6
SBDIP
-40oC to +85oC CDP1851CD
- D40.6
Burn-In
CDP1851CDX CDP1851DX D40.6
Description
THE CDP1851 and CDP1851C are CMOS programmable two-
port I/Os designed for use as general-purpose I/O devices.
They are directly compatible with CDP1800-series micropro-
cessors functioning at maximum clock frequency. Each port
can be programmed in either byte-I/O or bit-programmable
modes for interfacing with peripheral devices such as printers
and keyboards.
Both ports A and B can be separately programmed to be 8-bit
input or output ports with handshaking control lines, RDY and
STROBE. Only port A can be programmed to be a bidirectional
port. This configuration provides a means for communicating
with a peripheral device or microprocessor system on a single
8-bit bus for both transmitting and receiving data. Handshaking
signals are provided to maintain proper bus access control.
Port A handshaking lines are used for input control and port B
handshaking lines are used for output; therefore port B must be
in the bit-programmable mode where handshaking is not used.
Ports A and B can be separately bit programmed so that each
individual line can be designated as an input or output line. The
handshaking lines may also be individually programmed as
input or output when port A is not in bidirectional mode.
The CDP1851 has a supply-voltage range of 4V to 10.5V, and
the CDP1851C has a range of 4V to 6.5V. Both types are sup-
plied in 40-lead dual-in-line plastic (E suffix) or hermetic
ceramic (D suffix) packages. The CDP1851C is also available
in chip form (H suffix).
Pinout
CDP1851, CDP1851C
(PDIP, SBDIP)
TOP VIEW
CLOCK 1
CS 2
RA0 3
RA1 4
BUS0 5
BUS1 6
BUS2 7
BUS3 8
BUS4 9
BUS5 10
BUS6 11
BUS7 12
CLEAR 13
A INT 14
B INT 15
B RDY 16
B
STROBE
17
B0 18
B1 19
VSS 20
40 VDD
39 RD/WE
38 WR/RE
37 TPB
36 A RDY
35
A
STROBE
34 A0
33 A1
32 A2
31 A3
30 A4
29 A5
28 A6
27 A7
26 B7
25 B6
24 B5
23 B4
22 B3
21 B2
CDP1851 Programming Modes
MODE
(8)
PORT A
DATA PINS
(2)
PORT A
HANDSHAKING
PINS
Input
Accept Input
Data
READY, STROBE
Output
Output Data
READY, STROBE
Bidirectional Transfer In-
Input Handshaking
(Port A Only) put/Output Data for Port A
Bit-Program- Programmed In- Programmed Individ-
mable
dividually as In- ually as Inputs or
puts or Outputs Outputs
(8)
PORT B
DATA PINS
(2)
PORT B
HANDSHAKING
PINS
Accept Input Data READY, STROBE
Output Data
READY, STROBE
Must be Previous- Output Handshaking
ly Set to Bit-Pro- for Port A
grammable Mode
Programmed Indi- Programmed Individ-
vidually as Inputs ually as Inputs or
or Outputs
Outputs
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-5
File Number 1056.2
1 page  
CDP1851, CDP1851C
Programming
Initialization and Controls
The CDP1851 PlO must be cleared by a low on the CLEAR
input during power-on to set it for programming. Once
programmed, modes can be changed without clearing
except when exiting the bit-programmable mode. A low on
the CLEAR input sets both ports to the input modes,
disables interrupts, unmasks all bit-programmed interrupt
bits, and resets the status register, A RDY, and B RDY.
Mode Setting
The control register must be sequentially loaded with the
appropriate mode set control bytes in order as shown in Table
1 (i.e. input mode then output mode, etc.). Port A is set with
the SET A bit = 1 and port B is set with the SET B bit = 1. If a
port is set to the bit-programmable mode, the bit-programming
control byte from Table 2 must be loaded. A bit is programmed
for output with the I/O bit = 1 and for input with the I/O bit = 0.
The STROBE and RDY lines may be programmed for input or
output with the STROBE/RDY control byte of Table 2. Input
data on the STROBE and RDY lines is detected by reading
the status register. When using the STROBE or RDY lines for
output, the control byte must be loaded every time output data
is to be changed. To program logical conditions that will gen-
erate an interrupt, the interrupt control byte of Table 3 must be
loaded. An interrupt mask of the eight I/O lines may be loaded
next, if bit D4 (mask follows) of the interrupt control byte = 1.
The I/O lines are masked if the corresponding bit of the inter-
rupt mask register is 1, otherwise it is monitored. Any combi-
nation of masked bits are permissible, except all bits masked
(mask = FF).
INT Enable Disable
To enable or disable the INT line in all modes, the interrupt
ENABLE/DISABLE byte must be loaded (see Table 4). Inter-
rupts can also be detected by reading the status register
(see Table 5). All interrupts should be disabled when
programming or false interrupts may occur. The INT outputs
are open drain NMOS devices that allow wired O Ring (use
10K pull-up registers).
GENERATE CLEAR PULSE
AT PIN 13
SET PORTS A AND B
TO INPUT, OUTPUT, OR
BIT-PROGRAMMABLE MODE
USING TABLE 1
REPEAT FOR EACH
BIT-PROGRAMMABLE
PORT
REPEAT FOR EACH
BIT-PROGRAMMABLE
PORT
YES
PERFORM FOLLOWING
SEQUENCE BEFORE
PROGRAMMING PORT A TO
BIDIRECTIONAL MODE
IS
EITHER PORT
SET TO THE
BIT-PROGRAMMABLE
MODE 3
NO
SET BIT DIRECTION
USING TABLE 2
WILL
INTERRUPTS
BE USED FOR
BIT-PROGRAMMED
PORT?
NO
NOW SET PORT A TO
BIDIRECTIONAL MODE,
IF DESIRED
SET MASTER INTERRUPT
ENABLE/DISABLE
USING TABLE 4
MAIN PROGRAM
YES
SET BIT LOGICAL
CONDITIONS AND
MASKING USING
TABLE 3
NOTES:
FIGURE 3. A FLOW CHART GUIDE TO CDP1851 MODE PROGRAMMING
1. STROBE/READY I/O Control Byte (Table 2) is also used to output data to STROBE and READY lines when bit-programmed.
2. Status register (Table 2) is used to input data from STROBE and READY lines when bit-programmed.
3. Interrupt status is also read from status register.
4-9
5 Page 
CDP1851, CDP1851C
Test Circuit and Waveforms
VDD
A INT
B INT
CDP1851
1kΩ
1kΩ
50pF
A
50pF
B
INPUT
SIGNAL
A, B
50%
10%
tPINT
tWINT
50%
50%
tSTINT
FIGURE 5. INTERRUPT SIGNAL PROPAGATION DELAY TIME TEST CIRCUIT AND WAVEFORMS
RDY
INT
STROBE
DATA-IN
tSTRDY
tWST
tSTINT
tDIST
tHSTDI
tTPRDY
tPINT
tWTPB
TPB
CLOCK = (TPA)
tWCL
tCSCL
CS
WR/RE = (MRD)
tWRCL
RD/WE = (MWR)
MEMORY SPACE
tRWCL
tHCSCL
RD/WE = (MRD)
WR/RE = (TPB)
I/O SPACE
RA1/RA0
DATA BUS
tHATPB
VALID PORT ADDRESS
IO OR II
tADA
tHADOH
FIGURE 6. INPUT MODE TIMING WAVEFORMS
4-15
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet CDP1851C.PDF ] | |
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