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PDF CDP1824C Data sheet ( Hoja de datos )

Número de pieza CDP1824C
Descripción 32-Word x 8-Bit Static RAM
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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No Preview Available ! CDP1824C Hoja de datos, Descripción, Manual

CDP1824,
CDP1824C
March 1997
32-Word x 8-Bit Static RAM
Features
Description
• Fast Access Time
- VDD = 5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710ns
- VDD = 10V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320ns
• No Precharge or Clock Required
The CDP1824 and CDP1824C are 32-word x 8-bit fully static
CMOS random-access memories for use in CDP-1800
series microprocessor systems. These parts are compatible
with the CDP1802 microprocessor and will interface directly
without additional components.
The CDP1824 is fully decoded and does not require a pre-
charge or clocking signal for proper operation. It has
common input and output and is operated from a single
voltage supply. The MRD signal (output disable control)
enables the three-state output drivers, and overrides the
MWR signal. A CS input is provided for memory expansion.
The CDP1824C is functionally identical to the CDP1824.
The CDP1824 has an operating range of 4V to 10.5V, and
the CDP1824C has an operating voltage range of 4V to
6.5V. The CDP1824 and CDP1824C are supplied in 18 lead
hermetic dual-in-line ceramic packages (D suffix), and in 18
lead dual-in-line plastic packages (E suffix).
Ordering Information
5V
CDP1824CE
CDP1824CEX
CDP1824CD
10V
CDP1824E
CDP1824EX
CDP1824D
Pinout
CDP1824, CDP1824C (PDIP, SBDIP)
TOP VIEW
MA4 1
MA3 2
MA2 3
MA1 4
MA0 5
BUS 7 6
BUS 6 7
BUS 5 8
VSS 9
18 VDD
17 MWR
16 MRD
15 CS
14 BUS 0
13 BUS 1
12 BUS 2
11 BUS 3
10 BUS 4
PACKAGE
PDIP
Burn-In
SBDIP
TEMPERATURE RANGE
-40oC to +85oC
-40oC to +85oC
PKG. NO.
E18.3
E18.3
D18.3
OPERATIONAL MODES
FUNCTION CS MRD MWR DATA PINS STATUS
READ
0 0 X Output: High/Low Dependent
on Data
WRITE
0 1 0 Input: Output Disabled
Not
Selected
1 X X Output Disabled:
High-Impedance State
Standby
0 1 1 Output Disabled:
High-Impedance State
Logic 1 = High Logic 0 = Low X = Don’t Care
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
6-37
File Number 1103.2

1 page




CDP1824C pdf
CDP1824, CDP1824C
Data Retention Specifications at TA = -40oC to +85oC; See Figure 3
TEST CONDITIONS
PARAMETER
Data Retention Voltage
Data Retention Quiescent Current
Chip Deselect to Data Retention
Time
SYMBOL
VDR
IDD
tCDR
VDR = 2.5V
VDR = 2.5V
Recovery to Normal Operation Time
tRC
VDR = 2.5V
VDD
(V)
-
-
5
10
5
10
LIMITS
CDP1824
CDP1824C
MIN MAX MIN MAX
2.5 - 2.5 -
- 10 - 40
600 - 600 -
300 - - -
600 - 600 -
300 - - -
UNITS
V
µA
ns
ns
ns
ns
MA4
MA3
MA2
MA1
MA0
3
4
5
21
ADDRESS
DECODER
32 X 8-BIT
ARRAY
SENSE
AMPL
17
MWR
CS 15
I/O BUFFERS
16
MRD
VDD = 18
VSS = 9
6 7 8 10 11 12 13 14
BUS BUS BUS BUS BUS BUS BUS BUS
76543210
FIGURE 4. FUNCTIONAL DIAGRAM
CPU/ROM SYSTEM
ADDRESS
RAM SYSTEM
MA0-MA7
TPA
MRD
MWR
CPU
CDP1802
BUS0-BUS7
MA0-MA7
TPA
MRD
ROM
CE0
BUS0-BUS7
MA0-MA7
MRD
MWR
RAM
CDP1824
CS
BUS0-BUS7
DATA
FIGURE 5. CDP1824 (128 X 8) MINIMUM SYSTEM (128 X 8)
6-41

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