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PDF CDP1823 Data sheet ( Hoja de datos )
| Número de pieza | CDP1823 | |
| Descripción | 128-Word x 8-Bit LSI Static RAM | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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March 1997
CDP1823,
CDP1823C
128-Word x 8-Bit
LSI Static RAM
Features
Description
• Fast Access Time
- VDD = 5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450ns
- VDD = 10V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250ns
• Common Data Inputs and Outputs
• Multiple Chip Select Inputs to Simplify Memory
System Expansion
Ordering Information
5V
CDP1823CE
CDP1823CD
PKG.
10V PACKAGE TEMP. RANGE NO.
CDP1823E PDIP
-40oC to +85oC E24.6
CDP1823D SBDIP
-40oC to +85oC D24.6
CDP1823CDX
-
Burn-In
D24.6
The CDP1823 and CDP1823C are 128-word by 8-bit CMOS
SOS static random-access memories. These memories are
compatible with general-purpose microprocessors. The two
memories are functionally identical. They differ in that the
CDP1823 has a recommended operating voltage range of
4V to 10.5V, and the CDP1823C has a recommended oper-
ating voltage range of 4V to 6.5V.
The CDP1823 memory has 8 common data input and data
output terminals for direct connection to a bidirectional data
bus and is operated from a single voltage supply. Five chip-
select inputs are provided to simplify memory-system expan-
sion. In order to enable the CDP1823, the chip-select inputs
CS2, CS3 and CS5 require a low input signal, and the chip-
select inputs CS1 and CS4 require a high input signal.
The MRD signal enables all 8 output drivers when in the low
state and should be in a high state during a write cycle.
After valid data appear at the output, the address inputs may
be changed immediately. Output data will be valid until either
the MRD signal goes high, the device is deselected, or tAA
(access time) after address changes.
Pinout
CDP1823, CDP1823C
(PDIP, SBDIP)
TOP VIEW
BUS 0 1
BUS 1 2
BUS 2 3
BUS 3 4
BUS 4 5
BUS 5 6
BUS 6 7
BUS 7 8
CS1 9
CS2 10
CS3 11
VSS 12
24 VDD
23 MA0
22 MA1
21 MA2
20 MA3
19 MA4
18 MA5
17 MA6
16 MWR
15 MRD
14 CS5
13 CS4
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
6-24
File Number 1198.2
1 page  
CDP1823, CDP1823C
Dynamic Electrical Specifications At TA = -40 to +85oC, VDD ±5%, tR, tF = 20ns, CL = 100pF
LIMITS
CDP1823
CDP1823C
PARAMETER
SYMBOL
VDD (NOTE 2) (NOTE 1)
(NOTE 2) (NOTE 1)
(V) MIN TYP MAX MIN TYP MAX
Write Cycle (See Figure 2)
Write Recovery
tWR 5 75
10 50
-
-
- 75 -
---
-
-
Write Cycle
tWC 5 400 -
10 225
-
- 400 -
---
-
-
Write Pulse Width
tWRW 5 200
10 100
-
-
- 200 -
---
-
-
Address Setup Time
tAS 5 125 -
10 75
-
- 125 -
---
-
-
Data Setup Time
tDS 5 100 -
10 75
-
- 100 -
---
-
-
Data Hold Time From MWR
tDH 5 75
10 50
-
-
- 75 -
---
-
-
NOTES:
1. Typical values are at TA = 25oC and nominal voltage.
2. Time required by a limit device to allow for the indicated function.
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADDRESS
CS1, CS4
tAS
tWC
tWR
CS2, CS3, CS5
MWR
BUS 0-7
tWRW
tDS
VALID DATA
NOTE:
1. MRD must be high during write operation.
FIGURE 2. WRITE CYCLE TIMING DIAGRAM
tDH
6-28
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet CDP1823.PDF ] | |
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