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PDF CDP1822 Data sheet ( Hoja de datos )
| Número de pieza | CDP1822 | |
| Descripción | 256-Word x 4-Bit LSI Static RAM | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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March 1997
CDP1822,
CDP1822C
256-Word x 4-Bit
LSI Static RAM
Features
Description
• Low Operating Current
- VDD = 5V, Cycle Time 1µs . . . . . . . . . . . . . . . . . . 8mA
• Industry Standard Pinout
• Two Chip-Select Inputs-Simple Memory Expansion
• Memory Retention for Standby Battery Voltage of 2V
Minimum
• Output-Disable for Common I/O Systems
• Three-State Data Output for Bus-Oriented Systems
• Separate Data Inputs and Outputs
Ordering Information
5V
CDP1822CE
10V
CDP1822E
PACKAGE
PDIP
TEMP. RANGE
-40oC to +85oC
PKG.
NO.
E22.4
CDP1822CEX CDP1822EX
CDP1822CD CDP1822D
Burn-In
E22.4
SBDIP -40oC to +85oC D22.4A
CDP1822CDX
-
Burn-In
D22.4A
The CDP1822 and CDP1822C are 256-word by 4-bit static
random-access memories designed for use in memory sys-
tems where high speed, low operating current, and simplicity
in use are desirable. The CDP1822 features high speed and
a wide operating voltage range. Both types have separate
data inputs and outputs and utilize single power supplies of
4V to 6.5V for the CDP1822C and 4V to 10.5V for the
CDP1822.
Two Chip-Select inputs are provided to simplify system
expansion. An Output Disable control provides Wire-OR
capability and is also useful in common Input/Output sys-
tems. The Output Disable input allows these RAMs to be
used in common data Input/Output systems by forcing the
output into a high-impedance state during a write operation
independent of the Chip-Select input condition. The output
assumes a high-impedance state when the Output Disable is
at high level or when the chip is deselected by CS1 and/or
CS2.
The high noise immunity of the CMOS technology is pre-
served in this design. For TTL interfacing at 5V operation,
excellent system noise margin is preserved by using an
external pull-up resistor at each input.
Pinout
CDP1822, CDP1822C
(PDIP, SBDIP)
TOP VIEW
A3 1
A2 2
A1 3
A0 4
A5 5
A6 6
A7 7
VSS 8
DI1 9
DO1 10
DI2 11
22 VDD
21 A4
20 R/W
19 CS1
18 O. D.
17 CS2
16 DO4
15 DI4
14 DO3
13 DI3
12 DO2
OPERATIONAL MODES
INPUTS
MODE
Read
CHIP
SELECT
1
(CS1)
0
CHIP
SELECT
2
(CS2)
1
OUTPUT
DISABLE
(OD)
0
READ/
WRITE
(R/W)
1
OUTPUT
Read
Write
01
0 0 Data In
Write
01
1 0 High
Imped-
ance
Standby
1
X
X X High
Imped-
ance
Standby
X
0
X X High
Imped-
ance
Output
Disable
X
X
1 X High
Imped-
ance
NOTE:
Logic 1 = High, Logic 0 = Low, X = Don’t Care.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
6-11
File Number 1074.2
1 page  
CDP1822, CDP1822C
Dynamic Electrical Specifications At TA + -40 to +85oC, VDD ±5%, Input tR, tF = 20ns, VIH = 0.7 VDD, VIL = 0.3 VDD,
CL = 100 pF. (Continued)
TEST
CONDITIONS
CD1822
LIMITS
CDP1822C
PARAMETER
VDD
(V)
(NOTE 1) (NOTE 2)
(NOTE 1) (NOTE 2)
MIN TYP MAX MIN
TYP
MAX
UNITS
Chip-Select 1 Hold
tCS1H
5
10
0 - -0
0 - -0
- - ns
- - ns
Chip-Select 2 Hold
tCS2H
5
10
0 - -0
0 - -0
- - ns
- - ns
Output Disable Set-Up
tODS
5
200 - - 200
-
- ns
10 110 - - -
- - ns
NOTES:
1. Time required by a limit device to allow for indicated function.
2. Typical values are for TA = 25oC and nominal VDD.
A0-A7
CHIP-SELECT 1
tCSIS
tWC
tWR
tCSIH
CHIP-SELECT 2
OUTPUT DISABLE
DI1-DI4
(NOTE)
tODS
tCS2S
tCS2H
tDS
DATA IN STABLE
tDH
READ/WRITE
tWRW
tAS
DON’T CARE
NOTE: tODS is required for common I/O operation only. For separate I/O operations, output disable is don’t care.
FIGURE 2. WRITE CYCLE TIME WAVEFORMS
6-15
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet CDP1822.PDF ] | |
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