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PDF 93LC46C Data sheet ( Hoja de datos )
| Número de pieza | 93LC46C | |
| Descripción | 1K Microwire Compatible Serial EEPROM | |
| Fabricantes | Microchip | |
| Logotipo |  |
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93AA46A/B/C, 93LC46A/B/C,
93C46A/B/C
1K Microwire Compatible Serial EEPROM
Device Selection Table
Part Number
93AA46A
93AA46B
93LC46A
93LC46B
93C46A
93C46B
93AA46C
93LC46C
93C46C
VCC Range
1.8-5.5
1.8-5-5
2.5-5.5
2.5-5.5
4.5-5.5
4.5-5.5
1.8-5.5
2.5-5.5
4.5-5.5
ORG Pin
No
No
No
No
No
No
Yes
Yes
Yes
Features:
• Low-Power CMOS Technology
• ORG Pin to Select Word Size for ‘46C’ Version
• 128 x 8-bit Organization ‘A’ Devices (no ORG)
• 64 x 16-bit Organization ‘B’ Devices (no ORG)
• Self-Timed Erase/Write Cycles (including
Auto-Erase)
• Automatic Erase All (ERAL) Before Write All
(WRAL)
• Power-On/Off Data Protection Circuitry
• Industry Standard 3-Wire Serial I/O
• Device Status Signal (Ready/Busy)
• Sequential Read Function
• 1,000,000 Erase/Write Cycles
• Data Retention > 200 Years
• Pb-free and RoHS Compliant
• Temperature Ranges Supported:
- Industrial (I) -40°C to +85°C
- Automotive (E) -40°C to +125°C
Word Size Temp Ranges
Packages
8-bit
16-bit
8-bit
16-bit
8-bit
16-bit
8- or 16-bit
8- or 16-bit
8- or 16-bit
I P, SN, ST, MS, OT, MC, MN
I P, SN, ST, MS, OT, MC, MN
I, E P, SN, ST, MS, OT, MC, MN
I, E P, SN, ST, MS, OT, MC, MN
I, E P, SN, ST, MS, OT, MC, MN
I, E P, SN, ST, MS, OT, MC, MN
I P, SN, ST, MS, MC, MN
I, E P, SN, ST, MS, MC, MN
I, E P, SN, ST, MS, MC, MN
Pin Function Table
Name
Function
CS
CLK
DI
DO
VSS
NC
ORG
VCC
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
No internal connection
Memory Configuration
Power Supply
Description:
The Microchip Technology Inc. 93XX46A/B/C devices
are 1Kbit low-voltage serial Electrically Erasable
PROMs (EEPROM). Word-selectable devices such as
the 93AA46C, 93LC46C or 93C46C are dependent
upon external logic levels driving the ORG pin to set
word size. For dedicated 8-bit communication, the
93AA46A, 93LC46A or 93C46A devices are available,
while the 93AA46B, 93LC46B and 93C46B devices
provide dedicated 16-bit communication. Advanced
CMOS technology makes these devices ideal for low-
power, nonvolatile memory applications. The entire
93XX Series is available in standard packages includ-
ing 8-lead PDIP and SOIC, and advanced packaging
including 8-lead MSOP, 6-lead SOT-23, 8-lead
2x3 DFN/TDFN and 8-lead TSSOP. All packages are
Pb-free (Matte Tin) finish.
2002-2011 Microchip Technology Inc.
DS21749J-page 1
1 page  
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
FIGURE 1-1:
SYNCHRONOUS DATA TIMING
CS VIH
VIL
VIH
CLK
VIL
TDIS
VIH
DI
VIL
TCSS
DO
(Read)
VOH
VOL
DO
(Program)
VOH
VOL
TSV
Note: TSV is relative to CS.
TCKH
TDIH
TPD
TCKL
Status Valid
TCSH
TPD
TCZ
TCZ
TABLE 1-3: INSTRUCTION SET FOR X16 ORGANIZATION (93XX46B OR 93XX46C WITH ORG = 1)
Instruction SB Opcode
Address
Data In Data Out Req. CLK Cycles
ERASE
ERAL
EWDS
EWEN
READ
WRITE
WRAL
1 11 A5 A4 A3 A2 A1 A0 — (RDY/BSY)
1 00 1 0 X X X X — (RDY/BSY)
1 00 0 0 X X X X —
High-Z
1 00 1 1 X X X X —
High-Z
1 10 A5 A4 A3 A2 A1 A0 —
D15 - D0
1 01 A5 A4 A3 A2 A1 A0 D15 - D0 (RDY/BSY)
1 00 0 1 X X X X D15 - D0 (RDY/BSY)
9
9
9
9
25
25
25
TABLE 1-4: INSTRUCTION SET FOR X8 ORGANIZATION (93XX46A OR 93XX46C WITH ORG = 0)
Instruction SB Opcode
Address
Data In Data Out Req. CLK Cycles
ERASE
ERAL
EWDS
EWEN
READ
WRITE
WRAL
1
11 A6 A5 A4 A3 A2 A1 A0 —
(RDY/BSY)
1 00 1 0 X X X X X — (RDY/BSY)
1 00 0 0 X X X X X —
High-Z
1 00 1 1 X X X X X —
High-Z
1 10 A6 A5 A4 A3 A2 A1 A0 —
D7 - D0
1 01 A6 A5 A4 A3 A2 A1 A0 D7 - D0 (RDY/BSY)
1 00 0 1 X X X X X D7 - D0 (RDY/BSY)
10
10
10
10
18
18
18
2002-2011 Microchip Technology Inc.
DS21749J-page 5
5 Page 
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
2.9 Write All (WRAL)
The Write All (WRAL) instruction will write the entire
memory array with the data specified in the command.
For 93AA46A/B/C and 93LC46A/B/C devices, after the
last data bit is clocked into DI, the falling edge of CS
initiates the self-timed auto-erase and programming
cycle. For 93C46A/B/C devices, the self-timed auto-
erase and programming cycle is initiated by the rising
edge of CLK on the last data bit. Clocking of the CLK
pin is not necessary after the device has entered the
WRAL cycle. The WRAL command does include an
automatic ERAL cycle for the device. Therefore, the
WRAL instruction does not require an ERAL instruction,
but the chip must be in the EWEN status.
The DO pin indicates the Ready/Busy status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL).
Note:
After the Write All cycle is complete,
issuing a Start bit and then taking CS low
will clear the Ready/Busy status from DO.
VCC must be 4.5V for proper operation of WRAL.
FIGURE 2-10:
CS
WRAL TIMING FOR 93AA AND 93LC DEVICES
TCSL
CLK
DI 1 0 0 0 1 x ••• x Dx ••• D0
DO High-Z
VCC must be 4.5V for proper operation of WRAL.
TSV TCZ
Busy
TWL
Ready
HIGH-Z
FIGURE 2-11:
CS
WRAL TIMING FOR 93C DEVICES
TCSL
CLK
DI 1 0 0 0 1 x ••• x Dx ••• D0
TSV TCZ
DO High-Z
Busy Ready
HIGH-Z
TWL
2002-2011 Microchip Technology Inc.
DS21749J-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 93LC46C.PDF ] | |
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