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PDF IS45S83200J Data sheet ( Hoja de datos )

Número de pieza IS45S83200J
Descripción 256Mb SYNCHRONOUS DRAM
Fabricantes ISSI 
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IS42S83200J, IS42S16160J
IS45S83200J, IS45S16160J
32Meg x 8, 16Meg x16
256Mb SYNCHRONOUS DRAM
ADVANCED INFORMATION
MARCH 2013
FEATURES
• Clock frequency: 166, 143 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Internal bank for hiding row access/precharge
• Single Power supply: 3.3V + 0.3V
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• Auto Refresh (CBR)
• Self Refresh
• 8K refresh cycles every 32 ms (A2 grade) or
64 ms (commercial, industrial, A1 grade)
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and precharge
command
OPTIONS
• Package:
54-pin TSOP-II
54-ball BGA
• Operating Temperature Range:
Commercial (0oC to +70oC)
Industrial (-40oC to +85oC)
Automotive Grade A1 (-40oC to +85oC)
Automotive Grade A2 (-40oC to +105oC)
OVERVIEW
ISSI's 256Mb Synchronous DRAM achieves high-speed
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock input.
The 256Mb SDRAM is organized as follows.
IS42S83200G IS42S16160G
8M x 8 x 4 Banks 4M x16x4 Banks
54-pin TSOPII 54-pin TSOPII
54-ball BGA
54-ball BGA
KEY TIMING PARAMETERS
Parameter -6 -7 Unit
Clk Cycle Time
CAS Latency = 3
CAS Latency = 2
6 7 ns
10 7.5 ns
Clk Frequency
CAS Latency = 3
CAS Latency = 2
166 143 Mhz
100 133 Mhz
Access Time from Clock
CAS Latency = 3
5.4 5.4 ns
CAS Latency = 2
5.4 5.4 ns
ADDRESS TABLE
Parameter
32M x 8
Configuration
8M x 8 x 4
banks
Refresh Count
Com./Ind.
A1
A2
8K/64ms
8K/64ms
8K/32ms
Row Addresses
A0-A12
Column Addresses
A0-A9
Bank Address Pins
BA0, BA1
Auto Precharge Pins
A10/AP
16M x 16
4M x 16 x 4
banks
8K/64ms
8K/64ms
8K/32ms
A0-A12
A0-A8
BA0, BA1
A10/AP
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time with-
out notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain
the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such ap-
plications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com 1
Rev. 00B
3/19/2013

1 page




IS45S83200J pdf
IS42S83200J, IS42S16160J
IS45S83200J, IS45S16160J
PIN CONFIGURATION
54-ball TF-BGA for x8 (Top View) (8.00 mm x 8.00 mm Body, 0.8 mm Ball Pitch)
package code: B
1 2 3 4 5 6 7 8 9
A
B VSS DQ7 VSSQ
C NC DQ6 VDDQ
D NC DQ5 VSSQ
E NC DQ4 VDDQ
F NC NC VSS
G DQM CLK CKE
H A12 A11 A9
J A8 A7 A6
VSS A5 A4
VDDQ DQ0 VDD
VSSQ DQ1 NC
VDDQ DQ2 NC
VSSQ DQ3 NC
VDD NC NC
CAS RAS WE
BA0 BA1 CS
A0 A1 A10
A3 A2 VDD
PIN DESCRIPTIONS
A0-A12
Row Address Input
A0-A9
Column Address Input
BA0, BA1
Bank Select Address
DQ0 to DQ7 Data I/O
CLK
System Clock Input
CKE
Clock Enable
CS
Chip Select
RAS
Row Address Strobe Command
CAS Column Address Strobe Command
WE Write Enable
DQM Data Input/Output Mask
Vdd Power
Vss Ground
Vddq Power Supply for I/O Pin
Vssq Ground for I/O Pin
NC No Connection
Integrated Silicon Solution, Inc. — www.issi.com 5
Rev. 00B
3/19/2013

5 Page





IS45S83200J arduino
IS42S83200J, IS42S16160J
IS45S83200J, IS45S16160J
FUNCTIONAL TRUTH TABLE
Current State
CS RAS CAS WE
Address
Command Action
Idle
H X X X
X
DESL
Nop or Power Down(2)
L H H H
X
NOP
Nop or Power Down(2)
L H H L
X
BST
Nop or Power Down
L H L H
BA, CA, A10
READ/READA ILLEGAL (3)
L H L L
A, CA, A10
WRIT/ WRITA ILLEGAL(3)
L L H H
BA, RA
ACT
Row activating
L L H L
BA, A10
PRE/PALL
Nop
L L L H
X
REF/SELF
Auto refresh or Self-refresh(4)
L L L L
OC, BA1=L
MRS
Mode register set
Row Active
H X X X
X
DESL
Nop
L H H H
X
NOP
Nop
L H H L
X
BST
Nop
L H L H
BA, CA, A10
READ/READA Begin read (5)
L H L
L
BA, CA, A10
WRIT/ WRITA Begin write (5)
L L
H H
BA, RA
ACT
ILLEGAL (3)
L L H L
BA, A10
PRE/PALL
Precharge
Precharge all banks(6)
L L
L H
X
REF/SELF
ILLEGAL
L L
L L
OC, BA
MRS
ILLEGAL
Read
H X X X
X
DESL
Continue burst to end to
Row active
L H H H
X
NOP
Continue burst to end Row
Row active
L H H L
X
BST
Burst stop, Row active
L H L
H
BA, CA, A10
READ/READA Terminate burst,
begin new read (7)
L H L
L
BA, CA, A10
WRIT/WRITA Terminate burst,
begin write (7,8)
L L H H
BA, RA
ACT
ILLEGAL (3)
L L H L
BA, A10
PRE/PALL
Terminate burst
Precharging
L L L H
X
REF/SELF
ILLEGAL
L L L L
OC, BA
MRS
ILLEGAL
Write
H X X X
X
DESL
Continue burst to end
Write recovering
L H H H
X
NOP
Continue burst to end
Write recovering
L H H L
X
BST
Burst stop, Row active
L H L
H
BA, CA, A10
READ/READA Terminate burst, start read :
Determine AP (7,8)
L H L
L
BA, CA, A10
WRIT/WRITA Terminate burst, new write :
Determine AP (7)
L L H H
BA, RA
RA ACT
ILLEGAL (3)
L L H L
BA, A10
PRE/PALL
Terminate burst Precharging (9)
L L L H
X
REF/SELF
ILLEGAL
L L L
L
OC, BA
MRS
ILLEGAL
Note: H=Vih, L=Vil x= Vih or Vil, V = Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code
Integrated Silicon Solution, Inc. — www.issi.com 11
Rev. 00B
3/19/2013

11 Page







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