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PDF IS42RM16160E Data sheet ( Hoja de datos )
| Número de pieza | IS42RM16160E | |
| Descripción | 4M x 16Bits x 4Banks Mobile Synchronous DRAM | |
| Fabricantes | ISSI | |
| Logotipo |  |
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IS42/45SM/RM/VM16160E
4M x 16Bits x 4Banks Mobile Synchronous DRAM
Description
These IS42/45SM/RM/VM16160E are mobile 268,435,456 bits CMOS Synchronous DRAM organized as 4 banks of 4,194,304 words x 16
bits. These products are offering fully synchronous operation and are referenced to a positive edge of the clock. All inputs and outputs
are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve high bandwidth. All input
and output voltage levels are compatible with LVCMOS.
Features
JEDEC standard 3.3V, 2.5V, 1.8V power supply.
• Auto refresh and self refresh.
• All pins are compatible with LVCMOS interface.
• 8K refresh cycle / 64ms.
• Programmable Burst Length and Burst Type.
- 1, 2, 4, 8 or Full Page for Sequential Burst.
- 4 or 8 for Interleave Burst.
• Programmable CAS Latency : 2,3 clocks.
• All inputs and outputs referenced to the positive edge of the
system clock.
• Data mask function by DQM.
• Internal 4 banks operation.
• Burst Read Single Write operation.
• Special Function Support.
- PASR(Partial Array Self Refresh)
- Auto TCSR(Temperature Compensated Self Refresh)
- Programmable Driver Strength Control
• Full Strength or 3/4, 1/2, 1/4, 1/8 of Full Strength
- Deep Power Down Mode
• Automatic precharge, includes CONCURRENT Auto Precharge
Mode and controlled Precharge.
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its
products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services
described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information
and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or
effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to
its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Rev. 0C | May 2013
www.issi.com - [email protected]
1
1 page  
Figure3: Simplified State Diagram
IS42/45SM/RM/VM16160E
EXTENDED
MODE
REGISTER
SET
SELF
REFRESH
MODE
REGISTER
SET
MRS
IDLE
REF CBR
REFRESH
DEEP
POWER
DOWN
WRITE
WRITE
SUSPEND
CKE
CKE
WRITE
ROW
ACTIVE
CKE
CKE
POWER
DOWN
ACTIVE
POWER
DOWN
READ
WRITE
READ
READ
CKE
CKE
READ
SUSPEND
WRITE A
SUSPEND
CKE
CKE
WRITE A
READ A
CKE
CKE
READ A
SUSPEND
POWER
ON
PRECHARGE
PRE-
CHARGE
Rev. 0C | May 2013
www.issi.com - [email protected]
Automatic Sequence
Manual Input
5
5 Page 
IS42/45SM/RM/VM16160E
Table4: Command Truth Table
Function
Command Inhinit (NOP)
No Operation (NOP)
Mode Register Set
Extended Mode Register Set
Active (select bank and
activate row)
Read
Read with Autoprecharge
Write
Write with Autoprecharge
Precharge All Banks
Precharge Selected Bank
Burst Stop
Auto Refresh
Self Refresh Entry
Self Refresh Exit
Precharge Power Down Entry
Precharge Down Exit
Clock Suspend Entry
Clock Suspend Exit
Deep Power Down Entry
Deep Power Down Exit
CKEn-1
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L
H
L
H
L
CKEn /CS /RAS /CAS
XHX
X
XLH
H
XLL
L
XLL
L
XLL
H
XLH
L
XLH
L
XLH
L
XLH
L
XLL
H
XLL
H
HLH
H
HL L
L
LLL
L
HX
H
LH
X
H
HX
L
LH
X
H
HX
H
LH
X
H
HX
L
LV
X
V
HX
L LH
H
HX
/WE
X
H
L
L
H
H
H
L
L
L
L
L
H
H
X
H
X
H
X
H
X
V
L
DQM
X
X
X
X
X
L/H
L/H
L/H
L/H
X
X
X
X
X
ADDR
A10
X
X
OP CODE
OP CODE
Bank/Row
Bank/Col
Bank/Col
Bank/Col
Bank/Col
X
Bank
X
X
X
L
H
L
H
H
L
Note
4
4
5
5
5
5
3
3
XX2
XX
XX
XX
XX
XX6
XX
Note :
1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.
H: High Level, L: Low Level, X: Don't Care, V: Valid
2. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high and will put the device in the all banks idle state once
tXSR is met. Command Inhibit or NOP commands should be issued on any clock edges occuring during the tXSR period. A minimum
of two NOP commands must be provided during tXSR period.
3. During refresh operation, internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
4. A0-A12 define OP CODE written to the mode register, and BA must be issued 0 in the mode register set, and 1 in the extended
mode register set.
5. DQM “L” means the data Write/Ouput Enable and “H” means the Write inhibit/Output High-Z. Write DQM Latency is 0 CLK and Read
DQM Latency is 2 CLK.
6. Standard SDRAM parts assign this command sequence as Burst Terminate. For Bat Ram parts, the Burst Terminate command is
assigned to the Deep Power Down function.
Rev. 0C | May 2013
www.issi.com - [email protected]
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IS42RM16160E.PDF ] | |
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