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PDF IS41LV44052B Data sheet ( Hoja de datos )
| Número de pieza | IS41LV44052B | |
| Descripción | 4M x 4 (16-MBIT) DYNAMIC RAM | |
| Fabricantes | ISSI | |
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IS41LV44052B
4M x 4 (16-MBIT) DYNAMIC RAM
WITH FAST PAGE MODE
JANUARY 2010
FEATURES
• Fast Page Mode Access Cycle
• TTL compatible inputs and outputs
• Refresh Interval:
-- 2,048 cycles/32 ms
• Refresh Mode: RAS-Only,
CAS-before-RAS (CBR), and Hidden
• Single power supply:
3.3V ± 10%
• Byte Write and Byte Read operation via two CAS
• Industrial temperature range -40°C to 85°C
DESCRIPTION
The ISSI IS41LV44052B is a 4,194,304 x 4-bit high-performance
CMOS Dynamic Random Access Memory. The Fast Page
Mode allows 2,048 or 4096 random accesses within a
single row with access cycle time as short as 20 ns per
4-bit word.
These features make the IS41LV44052B ideally suited
for high-bandwidth graphics, digital signal processing,
high-performance computing systems, and peripheral
applications.
The IS41LV44052B is packaged in a 24-pin TSOP-II with
JEDEC standard pinouts.
PRODUCT SERIES OVERVIEW
Part No.
IS41LV44052B
Refresh
2K
Voltage
3.3V ± 10%
KEY TIMING PARAMETERS
Parameter
RAS Access Time (trac)
CAS Access Time (tcac)
Column Address Access Time (taa)
Fast Page Mode Cycle Time (tpc)
Read/Write Cycle Time (trc)
-50
50
13
25
20
84
-60 Unit
60 ns
15 ns
30 ns
25 ns
104 ns
PIN CONFIGURATION
24 (26) Pin TSOP-II
VCC
I/O0
I/O1
WE
RAS
*A11(NC)
1
2
3
4
5
6
A10
A0
A1
A2
A3
VCC
7
8
9
10
11
12
24 GND
23 I/O3
22 I/O2
21 CAS
20 OE
19 A9
18 A8
17 A7
16 A6
15 A5
14 A4
13 GND
PIN DESCRIPTIONS
A0-A10 Address Inputs (2K Refresh)
I/O0-3
Data Inputs/Outputs
WE Write Enable
OE Output Enable
RAS
Row Address Strobe
CAS
Column Address Strobe
Vcc Power
GND
Ground
NC No Connection
* A11 is NC for 2K Refresh devices.
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
12/21/09
1
1 page  
IS41LV44052B
ELECTRICAL CHARACTERISTICS(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol Parameter
Test Condition
Vcc Speed Min. Max. Unit
Iil
Input Leakage Current
Any input 0V ≤ Vin ≤ Vcc
Other inputs not under test = 0V
–5 5 µA
Iio
Output Leakage Current
Output is disabled (Hi-Z)
0V ≤ Vout ≤ Vcc
–5 5 µA
Voh
Output High Voltage Level
Ioh = –2.0 mA, Vcc = 3.3V
2.4 — V
Vol
Output Low Voltage Level
Iol = 2 mA, Vcc = 3.3V
— 0.4 V
Icc1 Standby Current: TTL
RAS, CAS ≥ Vih Commercial
Industrial
3.3V
3.3V
— 0.5 mA
— 2
Icc2 Standby Current: CMOS
RAS, CAS ≥ Vcc – 0.2V 3.3V
— 0.5 mA
Icc3
Operating Current:
RAS, CAS,
Random Read/Write(2,3)
Address Cycling, trc = trc (min.)
Average Power Supply Current
-50
-60
— 120 mA
— 110
Icc4
Operating Current:
RAS= Vil, CAS ≥ Vih
Fast Page Mode(2,3,4)
trc = trc (min.)
Average Power Supply Current
-50 — 90 mA
-60 — 80
Icc4
Refresh Current:
RAS Cycling, CAS ≥ Vih
RAS-Only(2,3)
trc = trc (min.)
Average Power Supply Current
-50
-60
— 120 mA
— 110
Icc5
Refresh Current:
RAS, CAS Cycling
CBR(2,3,5)
trc = trc (min.)
Average Power Supply Current
-50
-60
— 120 mA
— 110
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tref refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each Fast Page cycle.
5. Enables on-chip refresh and address counters.
Integrated Silicon Solution, Inc.
Rev. C
12/21/09
5
5 Page 
IS41LV44052B
FAST-PAGE-MODE EARLY WRITE CYCLE (OE = DON'T CARE)
RAS
tCRP
CAS
tASR
ADDRESS
Row
WE
I/O
tRAS
tRC
tRCD
tCSH
tRSH
tCAS tCLCH
tRAD
tRAH
tASC
tAR
tRAL
tCAH
tACH
Column
tWCR
tWCS
tCWL
tRWL
tWCH
tWP
tDHR
tDS
tDH
Valid Data
tRP
Row
Don’t Care
Integrated Silicon Solution, Inc.
Rev. C
12/21/09
11
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