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PDF EN25Q16A Data sheet ( Hoja de datos )

Número de pieza EN25Q16A
Descripción 16 Megabit Serial Flash Memory
Fabricantes Eon Silicon Solution 
Logotipo Eon Silicon Solution Logotipo



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EN25Q16A
EN25Q16A
16 Megabit Serial Flash Memory with 4Kbyte Uniform Sector
FEATURES
Single power supply operation
- Full voltage range: 2.7-3.6 volt
Serial Interface Architecture
- SPI Compatible: Mode 0 and Mode 3
16 Mbit Serial Flash
- 16 M-bit/2048 K-byte/8192 pages
- 256 bytes per programmable page
Standard, Dual or Quad SPI
- Standard SPI: CLK, CS#, DI, DO, WP#
- Dual SPI: CLK, CS#, DQ0, DQ1, WP#
- Quad SPI: CLK, CS#, DQ0, DQ1, DQ2, DQ3
High performance
- 104MHz clock rate for one data bit
- 80MHz clock rate for two data bits
- 80MHz clock rate for four data bits
Low power consumption
- 12 mA typical active current
- 1 μA typical power down current
Uniform Sector Architecture:
- 512 sectors of 4-Kbyte
- 32 blocks of 64-Kbyte
- Any sector or block can be erased individually
Software and Hardware Write Protection:
- Write Protect all or portion of memory via
software
- Enable/Disable protection with WP# pin
High performance program/erase speed
- Page program time: 1.3ms typical
- Sector erase time: 60ms typical
- Block erase time 400ms typical
- Chip erase time: 12 seconds typical
Lockable 512 byte OTP security sector
Minimum 100K endurance cycle
Package Options
- 8 pins SOP 150mil body width
- 8 pins SOP 200mil body width
- 8 contact VDFN
- 8 pins PDIP
- All Pb-free packages are RoHS compliant
Industrial temperature Range
GENERAL DESCRIPTION
The EN25Q16A is a 16-Megabit (2048K-byte) Serial Flash memory, with advanced write protection
mechanisms. The EN25Q16A supports the standard Serial Peripheral Interface (SPI), and a high
performance Dual/Quad output as well as Dual/Quad I/O using SPI pins: Serial Clock, Chip Select,
Serial DQ0(DI), DQ1(DO), DQ2(WP#) and DQ3(NC). SPI clock frequencies of up to 80MHz are
supported allowing equivalent clock rates of 160MHz for Dual Output and 320MHz for Quad Output
when using the Dual/Quad Output Fast Read instructions. The memory can be programmed 1 to 256
bytes at a time, using the Page Program instruction.
The EN25Q16A is designed to allow either single Sector/Block at a time or full chip erase operation. The
EN25Q16A can be configured to protect part of the memory as the software protected mode. The
device can sustain a minimum of 100K program/erase cycles on each sector or block.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
1
©2004 Eon Silicon Solution, Inc.,
Rev. E, Issue Date: 2011/07/14
www.eonssi.com

1 page




EN25Q16A pdf
EN25Q16A
MEMORY ORGANIZATION
The memory is organized as:
z 2,097,152 bytes
z Uniform Sector Architecture
32 blocks of 64-Kbyte
512 sectors of 4-Kbyte
z 8192 pages (256 bytes each)
Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector,
Block or Chip Erasable but not Page Erasable.
Table 2. Uniform Block Sector Architecture
Block
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Sector
511
496
495
480
479
464
463
448
447
432
431
416
415
400
399
384
383
368
367
352
351
336
335
320
319
304
303
288
287
272
271
256
255
240
Address range
1FF000h
1FFFFFh
1F0000h
1EF000h
1F0FFFh
1EFFFFh
1E0000h
1DF000h
1E0FFFh
1DFFFFh
1D0000h
1CF000h
1D0FFFh
1CFFFFh
1C0000h
1BF000h
1C0FFFh
1BFFFFh
1B0000h
1AF000h
1B0FFFh
1AFFFFh
1A0000h
19F000h
1A0FFFh
19FFFF
190000h
18F000h
190FFFh
18FFFFh
180000h
17F000h
180FFFh
17FFFFh
170000h
16F000h
170FFFh
16FFFFh
160000
15F000
160FFFh
15FFFFh
150000h
14F000h
150FFFh
14FFFFh
140000h
13F000h
140FFFh
13FFFFh
130000h
12F000h
130FFFh
12FFFFh
120000h
11F000h
120FFFh
11FFFFh
110000h
10F000h
110FFFh
10FFFFh
100000h
0FF000h
100FFFh
0FFFFFh
0F0000h
0F0FFFh
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
5
©2004 Eon Silicon Solution, Inc.,
Rev. E, Issue Date: 2011/07/14
www.eonssi.com

5 Page





EN25Q16A arduino
Table 4A. Instruction Set
EN25Q16A
Instruction Name
Byte 1
Code
Byte 2
Byte 3
EQPI
RSTQIO(1) /
Release Quad I/O or
Fast Read Enhanced
Mode
RSTEN
RST(2)
Write Enable
Write Disable / Exit
OTP mode
Read Status
Register
Write Status
Register
Page Program
Sector Erase / OTP
erase
Block Erase
38h
FFh
66h
99h
06h
04h
05h
01h
02h
20h
D8h
(S7-S0)(3)
S7-S0
A23-A16
A23-A16
A23-A16
A15-A8
A15-A8
A15-A8
Chip Erase
C7h/ 60h
Deep Power-down
Release from Deep
Power-down, and
read Device ID
Release from Deep
Power-down
Manufacturer/
Device ID
Read Identification
Enter OTP mode
B9h
ABh
90h
9Fh
3Ah
dummy
dummy
dummy
(M7-M0)
dummy
(ID15-ID8)
Byte 4 Byte 5 Byte 6
A7-A0
A7-A0
A7-A0
D7-D0
Next byte
dummy (ID7-ID0)
00h
01h
(ID7-ID0)
(M7-M0)
(ID7-ID0)
(7)
(ID7-ID0)
(M7-M0)
n-Bytes
continuous(4)
continuous
(5)
(6)
Notes:
1. Device accepts eight-clocks command in Standard SPI mode, or two-clocks command in Quad SPI mode
2. RST command only executed if RSTEN command is executed first. Any intervening command will disable Reset.
3. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate data being read from the
device on the DO pin.
4. The Status Register contents will repeat continuously until CS# terminate the instruction.
5. The Device ID will repeat continuously until CS# terminate the instruction
6. The Manufacturer ID and Device ID bytes will repeat continuously until CS# terminate the instruction.
00h on Byte 4 starts with MID and alternate with DID, 01h on Byte 4 starts with DID and alternate with MID.
7. (M7-M0) : Manufacturer, (ID15-ID8) : Memory Type, (ID7-ID0) : Memory Capacity
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
11
©2004 Eon Silicon Solution, Inc.,
Rev. E, Issue Date: 2011/07/14
www.eonssi.com

11 Page







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